Annotation of sys/arch/vax/if/if_qereg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_qereg.h,v 1.7 2003/06/02 23:27:57 millert Exp $ */
2: /* $NetBSD: if_qereg.h,v 1.6 2001/06/19 13:42:18 wiz Exp $ */
3: /*
4: * Copyright (c) 1988 Regents of the University of California.
5: * All rights reserved.
6: *
7: * This code is derived from software contributed to Berkeley by
8: * Digital Equipment Corp.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. Neither the name of the University nor the names of its contributors
19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32: * SUCH DAMAGE.
33: *
34: * @(#)if_qereg.h 7.3 (Berkeley) 6/28/90
35: */
36:
37: /* @(#)if_qereg.h 1.2 (ULTRIX) 1/3/85 */
38:
39: /****************************************************************
40: * *
41: * Licensed from Digital Equipment Corporation *
42: * Copyright (c) *
43: * Digital Equipment Corporation *
44: * Maynard, Massachusetts *
45: * 1985, 1986 *
46: * All rights reserved. *
47: * *
48: * The Information in this software is subject to change *
49: * without notice and should not be construed as a commitment *
50: * by Digital Equipment Corporation. Digital makes no *
51: * representations about the suitability of this software for *
52: * any purpose. It is supplied "As Is" without expressed or *
53: * implied warranty. *
54: * *
55: * If the Regents of the University of California or its *
56: * licensees modify the software in a manner creating *
57: * derivative copyright rights, appropriate copyright *
58: * legends may be placed on the derivative work in addition *
59: * to that set forth above. *
60: * *
61: ****************************************************************/
62: /* ---------------------------------------------------------------------
63: * Modification History
64: *
65: * 13 Feb. 84 -- rjl
66: *
67: * Initial version of driver. derived from IL driver.
68: *
69: * ---------------------------------------------------------------------
70: */
71:
72: /*
73: * Digital Q-BUS to NI Adapter
74: */
75: #ifdef notdef
76: struct qedevice {
77: u_short qe_sta_addr[2]; /* Station address (actually 6 */
78: u_short qe_rcvlist_lo; /* Receive list lo address */
79: u_short qe_rcvlist_hi; /* Receive list hi address */
80: u_short qe_xmtlist_lo; /* Transmit list lo address */
81: u_short qe_xmtlist_hi; /* Transmit list hi address */
82: u_short qe_vector; /* Interrupt vector */
83: u_short qe_csr; /* Command and Status Register */
84: };
85: #endif
86:
87: /*
88: * Register offsets in register space.
89: */
90: #define QE_CSR_ADDR1 0
91: #define QE_CSR_ADDR2 2
92: #define QE_CSR_RCLL 4
93: #define QE_CSR_RCLH 6
94: #define QE_CSR_XMTL 8
95: #define QE_CSR_XMTH 10
96: #define QE_CSR_VECTOR 12
97: #define QE_CSR_CSR 14
98:
99: /*
100: * Command and status bits (csr)
101: */
102: #define QE_RCV_ENABLE 0x0001 /* Receiver enable */
103: #define QE_RESET 0x0002 /* Software reset */
104: #define QE_NEX_MEM_INT 0x0004 /* Non existent mem interrupt */
105: #define QE_LOAD_ROM 0x0008 /* Load boot/diag from rom */
106: #define QE_XL_INVALID 0x0010 /* Transmit list invalid */
107: #define QE_RL_INVALID 0x0020 /* Receive list invalid */
108: #define QE_INT_ENABLE 0x0040 /* Interrupt enable */
109: #define QE_XMIT_INT 0x0080 /* Transmit interrupt */
110: #define QE_ILOOP 0x0100 /* Internal loopback */
111: #define QE_ELOOP 0x0200 /* External loopback */
112: #define QE_STIM_ENABLE 0x0400 /* Sanity timer enable */
113: #define QE_POWERUP 0x1000 /* Tranceiver power on */
114: #define QE_CARRIER 0x2000 /* Carrier detect */
115: #define QE_RCV_INT 0x8000 /* Receiver interrupt */
116:
117: /*
118: * Transmit and receive ring discriptor ---------------------------
119: *
120: * The QNA uses the flag, status1 and the valid bit as a handshake/semiphore
121: * mechinism.
122: *
123: * The flag word is written on ( bits 15,15 set to 1 ) when it reads the
124: * descriptor. If the valid bit is set it considers the address to be valid.
125: * When it uses the buffer pointed to by the valid address it sets status word
126: * one.
127: */
128: struct qe_ring {
129: u_short qe_flag; /* Buffer utilization flags */
130: u_short qe_addr_hi;
131: u_short qe_addr_lo; /* Low order bits of address */
132: short qe_buf_len; /* Negative buffer length */
133: u_short qe_status1; /* Status word one */
134: u_short qe_status2; /* Status word two */
135: };
136:
137: /*
138: * High word address control bits.
139: */
140: #define QE_VALID 0x8000
141: #define QE_CHAIN 0x4000
142: #define QE_EOMSG 0x2000
143: #define QE_SETUP 0x1000
144: #define QE_ODDEND 0x0080
145: #define QE_ODDBEGIN 0x0040
146:
147: /*
148: * Status word definations (receive)
149: * word1
150: */
151: #define QE_OVF 0x0001 /* Receiver overflow */
152: #define QE_CRCERR 0x0002 /* CRC error */
153: #define QE_FRAME 0x0004 /* Framing alignment error */
154: #define QE_SHORT 0x0008 /* Packet size < 10 bytes */
155: #define QE_RBL_HI 0x0700 /* Hi bits of receive len */
156: #define QE_RUNT 0x0800 /* Runt packet */
157: #define QE_DISCARD 0x1000 /* Discard the packet */
158: #define QE_ESETUP 0x2000 /* Looped back setup or eloop */
159: #define QE_ERROR 0x4000 /* Receiver error */
160: #define QE_LASTNOT 0x8000 /* Not the last in the packet */
161: /* word2 */
162: #define QE_RBL_LO 0x00ff /* Low bits of receive len */
163:
164: /*
165: * Status word definations (transmit)
166: * word1
167: */
168: #define QE_CCNT 0x00f0 /* Collision count this packet */
169: #define QE_FAIL 0x0100 /* Heart beat check failure */
170: #define QE_ABORT 0x0200 /* Transmission abort */
171: #define QE_STE16 0x0400 /* Sanity timer default on */
172: #define QE_NOCAR 0x0800 /* No carrier */
173: #define QE_LOSS 0x1000 /* Loss of carrier while xmit */
174: /* word2 */
175: #define QE_TDR 0x3fff /* Time domain reflectometry */
176:
177: /*
178: * General constant definations
179: */
180: #define QEALLOC 0 /* Allocate an mbuf */
181: #define QENOALLOC 1 /* No mbuf allocation */
182: #define QEDEALLOC 2 /* Release an mbuf chain */
183:
184: #define QE_NOTYET 0x8000 /* Descriptor not in use yet */
185: #define QE_INUSE 0x4000 /* Descriptor being used by QNA */
186: #define QE_MASK 0xc000 /* Lastnot/error/used mask */
187:
188: /*
189: * Values for the length of the setup packet that control reception filter.
190: */
191: #define QE_SETUPLEN 128 /* Size of setup packet */
192: #define QE_ALLMULTI 1 /* Receive all multicasts */
193: #define QE_PROMISC 2 /* Receive all packets */
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