Annotation of sys/arch/vax/if/if_dereg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_dereg.h,v 1.4 2003/06/02 23:27:57 millert Exp $ */
2: /* $NetBSD: if_dereg.h,v 1.3 1996/04/08 18:34:55 ragge Exp $ */
3:
4: /*
5: * Copyright (c) 1982, 1986 Regents of the University of California.
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. Neither the name of the University nor the names of its contributors
17: * may be used to endorse or promote products derived from this software
18: * without specific prior written permission.
19: *
20: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30: * SUCH DAMAGE.
31: *
32: * @(#)if_dereg.h 7.3 (Berkeley) 6/28/90
33: */
34:
35: /*
36: * DEC DEUNA interface
37: */
38: struct dedevice {
39: union {
40: short p0_w;
41: char p0_b[2];
42: } u_p0;
43: #define pcsr0 u_p0.p0_w
44: #define pclow u_p0.p0_b[0]
45: #define pchigh u_p0.p0_b[1]
46: short pcsr1;
47: short pcsr2;
48: short pcsr3;
49: };
50:
51: /*
52: * PCSR 0 bit descriptions
53: */
54: #define PCSR0_SERI 0x8000 /* Status error interrupt */
55: #define PCSR0_PCEI 0x4000 /* Port command error interrupt */
56: #define PCSR0_RXI 0x2000 /* Receive done interrupt */
57: #define PCSR0_TXI 0x1000 /* Transmit done interrupt */
58: #define PCSR0_DNI 0x0800 /* Done interrupt */
59: #define PCSR0_RCBI 0x0400 /* Receive buffer unavail intrpt */
60: #define PCSR0_FATI 0x0100 /* Fatal error interrupt */
61: #define PCSR0_INTR 0x0080 /* Interrupt summary */
62: #define PCSR0_INTE 0x0040 /* Interrupt enable */
63: #define PCSR0_RSET 0x0020 /* DEUNA reset */
64: #define PCSR0_CMASK 0x000f /* command mask */
65:
66: #define PCSR0_BITS "\20\20SERI\17PCEI\16RXI\15TXI\14DNI\13RCBI\11FATI\10INTR\7INTE\6RSET"
67:
68: /* bits 0-3 are for the PORT_COMMAND */
69: #define CMD_NOOP 0x0
70: #define CMD_GETPCBB 0x1 /* Get PCB Block */
71: #define CMD_GETCMD 0x2 /* Execute command in PCB */
72: #define CMD_STEST 0x3 /* Self test mode */
73: #define CMD_START 0x4 /* Reset xmit and receive ring ptrs */
74: #define CMD_BOOT 0x5 /* Boot DEUNA */
75: #define CMD_PDMD 0x8 /* Polling demand */
76: #define CMD_TMRO 0x9 /* Sanity timer on */
77: #define CMD_TMRF 0xa /* Sanity timer off */
78: #define CMD_RSTT 0xb /* Reset sanity timer */
79: #define CMD_STOP 0xf /* Suspend operation */
80:
81: /*
82: * PCSR 1 bit descriptions
83: */
84: #define PCSR1_XPWR 0x8000 /* Transceiver power BAD */
85: #define PCSR1_ICAB 0x4000 /* Interconnect cabling BAD */
86: #define PCSR1_STCODE 0x3f00 /* Self test error code */
87: #define PCSR1_PCTO 0x0080 /* Port command timed out */
88: #define PCSR1_ILLINT 0x0040 /* Illegal interrupt */
89: #define PCSR1_TIMEOUT 0x0020 /* Timeout */
90: #define PCSR1_POWER 0x0010 /* Power fail */
91: #define PCSR1_RMTC 0x0008 /* Remote console reserved */
92: #define PCSR1_STMASK 0x0007 /* State */
93:
94: /* bit 0-3 are for STATE */
95: #define STAT_RESET 0x0
96: #define STAT_PRIMLD 0x1 /* Primary load */
97: #define STAT_READY 0x2
98: #define STAT_RUN 0x3
99: #define STAT_UHALT 0x5 /* UNIBUS halted */
100: #define STAT_NIHALT 0x6 /* NI halted */
101: #define STAT_NIUHALT 0x7 /* NI and UNIBUS Halted */
102:
103: #define PCSR1_BITS "\20\20XPWR\17ICAB\10PCTO\7ILLINT\6TIMEOUT\5POWER\4RMTC"
104:
105: /*
106: * Port Control Block Base
107: */
108: struct de_pcbb {
109: short pcbb0; /* function */
110: short pcbb2; /* command specific */
111: short pcbb4;
112: short pcbb6;
113: };
114:
115: /* PCBB function codes */
116: #define FC_NOOP 0x00 /* NO-OP */
117: #define FC_LSUADDR 0x01 /* Load and start microaddress */
118: #define FC_RDDEFAULT 0x02 /* Read default physical address */
119: #define FC_RDPHYAD 0x04 /* Read physical address */
120: #define FC_WTPHYAD 0x05 /* Write physical address */
121: #define FC_RDMULTI 0x06 /* Read multicast address list */
122: #define FC_WTMULTI 0x07 /* Read multicast address list */
123: #define FC_RDRING 0x08 /* Read ring format */
124: #define FC_WTRING 0x09 /* Write ring format */
125: #define FC_RDCNTS 0x0a /* Read counters */
126: #define FC_RCCNTS 0x0b /* Read and clear counters */
127: #define FC_RDMODE 0x0c /* Read mode */
128: #define FC_WTMODE 0x0d /* Write mode */
129: #define FC_RDSTATUS 0x0e /* Read port status */
130: #define FC_RCSTATUS 0x0f /* Read and clear port status */
131: #define FC_DUMPMEM 0x10 /* Dump internal memory */
132: #define FC_LOADMEM 0x11 /* Load internal memory */
133: #define FC_RDSYSID 0x12 /* Read system ID parameters */
134: #define FC_WTSYSID 0x13 /* Write system ID parameters */
135: #define FC_RDSERAD 0x14 /* Read load server address */
136: #define FC_WTSERAD 0x15 /* Write load server address */
137:
138: /*
139: * Unibus Data Block Base (UDBB) for ring buffers
140: */
141: struct de_udbbuf {
142: short b_tdrbl; /* Transmit desc ring base low 16 bits */
143: char b_tdrbh; /* Transmit desc ring base high 2 bits */
144: char b_telen; /* Length of each transmit entry */
145: short b_trlen; /* Number of entries in the XMIT desc ring */
146: short b_rdrbl; /* Receive desc ring base low 16 bits */
147: char b_rdrbh; /* Receive desc ring base high 2 bits */
148: char b_relen; /* Length of each receive entry */
149: short b_rrlen; /* Number of entries in the RECV desc ring */
150: };
151:
152: /*
153: * Transmit/Receive Ring Entry
154: */
155: struct de_ring {
156: short r_slen; /* Segment length */
157: short r_segbl; /* Segment address (low 16 bits) */
158: char r_segbh; /* Segment address (hi 2 bits) */
159: u_char r_flags; /* Status flags */
160: u_short r_tdrerr; /* Errors */
161: #define r_lenerr r_tdrerr
162: short r_rid; /* Request ID */
163: };
164:
165: #define XFLG_OWN 0x80 /* If 0 then owned by driver */
166: #define XFLG_ERRS 0x40 /* Error summary */
167: #define XFLG_MTCH 0x20 /* Address match on xmit request */
168: #define XFLG_MORE 0x10 /* More than one entry required */
169: #define XFLG_ONE 0x08 /* One collision encountered */
170: #define XFLG_DEF 0x04 /* Transmit deferred */
171: #define XFLG_STP 0x02 /* Start of packet */
172: #define XFLG_ENP 0x01 /* End of packet */
173:
174: #define XFLG_BITS "\10\10OWN\7ERRS\6MTCH\5MORE\4ONE\3DEF\2STP\1ENP"
175:
176: #define XERR_BUFL 0x8000 /* Buffer length error */
177: #define XERR_UBTO 0x4000 /* UNIBUS tiemout */
178: #define XERR_LCOL 0x1000 /* Late collision */
179: #define XERR_LCAR 0x0800 /* Loss of carrier */
180: #define XERR_RTRY 0x0400 /* Failed after 16 retries */
181: #define XERR_TDR 0x03ff /* TDR value */
182:
183: #define XERR_BITS "\20\20BUFL\17UBTO\15LCOL\14LCAR\13RTRY"
184:
185: #define RFLG_OWN 0x80 /* If 0 then owned by driver */
186: #define RFLG_ERRS 0x40 /* Error summary */
187: #define RFLG_FRAM 0x20 /* Framing error */
188: #define RFLG_OFLO 0x10 /* Message overflow */
189: #define RFLG_CRC 0x08 /* CRC error */
190: #define RFLG_STP 0x02 /* Start of packet */
191: #define RFLG_ENP 0x01 /* End of packet */
192:
193: #define RFLG_BITS "\10\10OWN\7ERRS\6FRAM\5OFLO\4CRC\2STP\1ENP"
194:
195: #define RERR_BUFL 0x8000 /* Buffer length error */
196: #define RERR_UBTO 0x4000 /* UNIBUS tiemout */
197: #define RERR_NCHN 0x2000 /* No data chaining */
198: #define RERR_MLEN 0x0fff /* Message length */
199:
200: #define RERR_BITS "\20\20BUFL\17UBTO\16NCHN"
201:
202: /* mode description bits */
203: #define MOD_HDX 0x0001 /* Half duplex mode */
204: #define MOD_LOOP 0x0004 /* Enable internal loopback */
205: #define MOD_DTCR 0x0008 /* Disables CRC generation */
206: #define MOD_DMNT 0x0200 /* Disable maintenance features */
207: #define MOD_ECT 0x0400 /* Enable collision test */
208: #define MOD_TPAD 0x1000 /* Transmit message pad enable */
209: #define MOD_DRDC 0x2000 /* Disable data chaining */
210: #define MOD_ENAL 0x4000 /* Enable all multicast */
211: #define MOD_PROM 0x8000 /* Enable promiscuous mode */
212:
213: struct de_buf {
214: struct ether_header db_head; /* header */
215: char db_data[ETHERMTU]; /* packet data */
216: int db_crc; /* CRC - on receive only */
217: };
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