Annotation of sys/arch/vax/bi/if_nireg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: if_nireg.h,v 1.2 2003/06/02 23:27:56 millert Exp $ */
! 2: /* $NetBSD: if_nireg.h,v 1.3 2001/08/20 12:20:07 wiz Exp $ */
! 3: /*
! 4: * Copyright (c) 1988 Regents of the University of California.
! 5: * All rights reserved.
! 6: *
! 7: * This code is derived from software contributed to Berkeley by
! 8: * Chris Torek.
! 9: *
! 10: * Redistribution and use in source and binary forms, with or without
! 11: * modification, are permitted provided that the following conditions
! 12: * are met:
! 13: * 1. Redistributions of source code must retain the above copyright
! 14: * notice, this list of conditions and the following disclaimer.
! 15: * 2. Redistributions in binary form must reproduce the above copyright
! 16: * notice, this list of conditions and the following disclaimer in the
! 17: * documentation and/or other materials provided with the distribution.
! 18: * 3. Neither the name of the University nor the names of its contributors
! 19: * may be used to endorse or promote products derived from this software
! 20: * without specific prior written permission.
! 21: *
! 22: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 25: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 26: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 27: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 28: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 29: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 30: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 31: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 32: * SUCH DAMAGE.
! 33: *
! 34: * @(#)nireg.h 7.3 (Berkeley) 6/28/90
! 35: */
! 36:
! 37: /*
! 38: * Registers for the DEBNA and DEBNK Ethernet interfaces
! 39: * (DEC calls these Network Interfaces, hence nireg.h)
! 40: */
! 41:
! 42: /*
! 43: * this seems to be intended to be more general, but I have no details,
! 44: * so it goes here for now
! 45: *
! 46: * BI Vax Port (BVP) stuff first:
! 47: */
! 48: #ifdef notdef
! 49: struct bvpregs {
! 50: u_long p_pcr; /* port control register */
! 51: u_long p_psr; /* port status register */
! 52: u_long p_per; /* port error register */
! 53: u_long p_pdr; /* port data register */
! 54: };
! 55:
! 56: /*
! 57: * BI node space registers
! 58: */
! 59: struct ni_regs {
! 60: struct biiregs ni_bi; /* BIIC registers, except GPRs */
! 61: struct bvpregs ni_tkp; /* tk50 port control via BIIC GPRs */
! 62: u_long ni_xxx[64]; /* unused */
! 63: u_long ni_rxcd; /* receive console data */
! 64: struct bvpregs ni_nip; /* NI port control via BCI3 GPRs */
! 65: u_long ni_pudr; /* power-up diagnostic register */
! 66: };
! 67: #endif
! 68:
! 69: #define NI_PCR 0x204
! 70: #define NI_PSR 0x208
! 71: #define NI_PER 0x20c
! 72: #define NI_PDR 0x210
! 73: #define NI_PUDR 0x204
! 74:
! 75: /* bits in PCR */
! 76: #define PCR_OWN 0x80
! 77: #define PCR_MFREEQ 0x000
! 78: #define PCR_DFREEQ 0x100
! 79: #define PCR_RFREEQ 0x200
! 80: #define PCR_IFREEQ 0x300
! 81: #define PCR_CMDQ0 PCR_MFREEQ
! 82: #define PCR_CMDQ1 PCR_DFREEQ
! 83: #define PCR_CMDQ2 PCR_RFREEQ
! 84: #define PCR_CMDQ3 PCR_IFREEQ
! 85: #define PCR_RESTART 11
! 86: #define PCR_FREEQNE 7
! 87: #define PCR_CMDQNE 6
! 88: #define PCR_SHUTDOWN 4
! 89: #define PCR_ENABLE 2
! 90: #define PCR_INIT 1
! 91:
! 92: /* bits in PSR */
! 93: #define PSR_OWN 0x80000000
! 94: #define PSR_STATE 0x00070000
! 95: #define PSR_STOPPED 0x00060000
! 96: #define PSR_ENABLED 0x00040000
! 97: #define PSR_INITED 0x00020000
! 98: #define PSR_UNDEF 0x00010000
! 99: #define PSR_RSQ 0x00000080
! 100: #define PSR_ERR 0x00000040
! 101:
! 102: /*
! 103: * The DEBNx uses a very weird (set of) structure(s) to communicate
! 104: * with something as simple as an ethernet controller. This is not
! 105: * very different to the way communication is done over CI with disks.
! 106: */
! 107:
! 108: /* Message packet */
! 109: struct ni_msg {
! 110: u_int32_t nm_forw;
! 111: u_int32_t nm_back;
! 112: u_int32_t nm_pad1;
! 113: u_int8_t nm_pad2;
! 114: u_int8_t nm_status;
! 115: u_int8_t nm_opcode;
! 116: u_int8_t nm_pad3;
! 117: u_int16_t nm_len;
! 118: u_int8_t nm_opcode2;
! 119: u_int8_t nm_status2;
! 120: u_int32_t nm_pad4;
! 121: u_int8_t nm_text[128];
! 122: };
! 123:
! 124: /* Datagram packet */
! 125: struct ni_dg {
! 126: u_int32_t nd_forw;
! 127: u_int32_t nd_back;
! 128: u_int32_t nd_pad1;
! 129: u_int8_t nd_pad2;
! 130: u_int8_t nd_status;
! 131: u_int8_t nd_opcode;
! 132: u_int8_t nd_pad3;
! 133: u_int16_t nd_len;
! 134: u_int16_t nd_status2;
! 135: u_int32_t nd_cmdref;
! 136: u_int32_t nd_ptdbidx;
! 137: struct {
! 138: u_int16_t _offset;
! 139: u_int16_t _len;
! 140: u_int16_t _index;
! 141: u_int16_t _key;
! 142: } bufs[NTXFRAGS];
! 143: };
! 144:
! 145: #define NIDG_CHAIN 0x8000
! 146:
! 147: /* NI parameter block */
! 148: struct ni_param {
! 149: u_int8_t np_dpa[8];
! 150: u_int8_t np_apa[8];
! 151: u_int8_t np_lsa[8];
! 152: u_int8_t np_bvc[8];
! 153: u_int16_t np_curaddr;
! 154: u_int16_t np_maxaddr;
! 155: u_int16_t np_curptt;
! 156: u_int16_t np_maxptt;
! 157: u_int16_t np_curfq;
! 158: u_int16_t np_maxfq;
! 159: u_int32_t np_sid;
! 160: u_int32_t np_mop;
! 161: u_int32_t np_flags;
! 162: u_int32_t np_rcto;
! 163: u_int32_t np_xmto;
! 164: };
! 165:
! 166: #define NP_ECT 0x01
! 167: #define NP_PAD 0x02
! 168: #define NP_BOO 0x04
! 169: #define NP_CAR 0x08
! 170: #define NP_ILP 0x10
! 171: #define NP_ELP 0x20
! 172: #define NP_DCRC 0x40
! 173: #define NP_THRU 0x80
! 174:
! 175: /* Protocol type definition block */
! 176: struct ni_ptdb {
! 177: u_int16_t np_type; /* Protocol type */
! 178: u_int8_t np_fque; /* Free queue */
! 179: u_int8_t np_flags; /* See below */
! 180: u_int32_t np_index; /* protocol type index */
! 181: u_int16_t np_adrlen; /* # of multicast addresses */
! 182: u_int16_t np_802; /* for IEEE 802 packets */
! 183: u_int8_t np_mcast[16][8];/* Multicast (direct match) array */
! 184: };
! 185:
! 186: #define PTDB_PROMISC 0x08
! 187: #define PTDB_802 0x10
! 188: #define PTDB_BDC 0x20
! 189: #define PTDB_UNKN 0x40
! 190: #define PTDB_AMC 0x80
! 191:
! 192: /* Buffer descriptor */
! 193: struct ni_bbd {
! 194: u_int16_t nb_status; /* Offset, valid etc */
! 195: u_int16_t nb_key;
! 196: u_int32_t nb_len; /* Buffer length */
! 197: u_int32_t nb_pte; /* start (vax) PTE for this buffer */
! 198: u_int32_t nb_pad;
! 199: };
! 200: #define NIBD_OFFSET 0x1ff
! 201: #define NIBD_VALID 0x8000
! 202:
! 203:
! 204: /* Free Queue Block */
! 205: struct ni_fqb {
! 206: u_int32_t nf_mlen;
! 207: u_int32_t nf_mpad;
! 208: u_int32_t nf_mforw;
! 209: u_int32_t nf_mback;
! 210: u_int32_t nf_dlen;
! 211: u_int32_t nf_dpad;
! 212: u_int32_t nf_dforw;
! 213: u_int32_t nf_dback;
! 214: u_int32_t nf_rlen;
! 215: u_int32_t nf_rpad;
! 216: u_int32_t nf_rforw;
! 217: u_int32_t nf_rback;
! 218: u_int32_t nf_ilen;
! 219: u_int32_t nf_ipad;
! 220: u_int32_t nf_iforw;
! 221: u_int32_t nf_iback;
! 222: };
! 223:
! 224: /* DEBNx specific part of Generic VAX Port */
! 225: struct ni_pqb {
! 226: u_int16_t np_veclvl; /* Interrupt vector + level */
! 227: u_int16_t np_node; /* Where to interrupt */
! 228: u_int32_t np_freeq;
! 229: u_int32_t np_vfqb; /* Free queue block pointer */
! 230: u_int32_t np_pad1[39];
! 231: u_int32_t np_bvplvl;
! 232: u_int32_t np_vpqb; /* Virtual address of Generic PQB */
! 233: u_int32_t np_vbdt; /* Virtual address of descriptors */
! 234: u_int32_t np_nbdr; /* Number of descriptors */
! 235: u_int32_t np_spt; /* System Page Table */
! 236: u_int32_t np_sptlen; /* System Page Table length */
! 237: u_int32_t np_gpt; /* Global Page Table */
! 238: u_int32_t np_gptlen; /* Global Page Table length */
! 239: u_int32_t np_mask;
! 240: u_int32_t np_pad2[67];
! 241: };
! 242:
! 243: /* "Generic VAX Port Control Block" whatever it means */
! 244: struct ni_gvppqb {
! 245: u_int32_t nc_forw0;
! 246: u_int32_t nc_back0;
! 247: u_int32_t nc_forw1;
! 248: u_int32_t nc_back1;
! 249: u_int32_t nc_forw2;
! 250: u_int32_t nc_back2;
! 251: u_int32_t nc_forw3;
! 252: u_int32_t nc_back3;
! 253: u_int32_t nc_forwr;
! 254: u_int32_t nc_backr;
! 255: struct ni_pqb nc_pqb; /* DEBNx specific part of struct */
! 256: };
! 257:
! 258:
! 259: /* BVP opcodes, should be somewhere else */
! 260: #define BVP_DGRAM 1
! 261: #define BVP_MSG 2
! 262: #define BVP_DGRAMI 3
! 263: #define BVP_DGRAMRX 33
! 264: #define BVP_MSGRX 34
! 265: #define BVP_DGRAMIRX 35
! 266:
! 267: /* NI-specific sub-opcodes */
! 268: #define NI_WSYSID 1
! 269: #define NI_RSYSID 2
! 270: #define NI_WPARAM 3
! 271: #define NI_RPARAM 4
! 272: #define NI_RCCNTR 5
! 273: #define NI_RDCNTR 6
! 274: #define NI_STPTDB 7
! 275: #define NI_CLPTDB 8
! 276:
! 277: /* bits in ni_pudr */
! 278: #define PUDR_TAPE 0x40000000 /* tk50 & assoc logic ok */
! 279: #define PUDR_PATCH 0x20000000 /* patch logic ok */
! 280: #define PUDR_VRAM 0x10000000 /* DEBNx onboard RAM ok */
! 281: #define PUDR_VROM1 0x08000000 /* uVax ROM 1 ok */ /* ? */
! 282: #define PUDR_VROM2 0x04000000 /* uVax ROM 2 ok */
! 283: #define PUDR_VROM3 0x02000000 /* uVax ROM 3 ok */
! 284: #define PUDR_VROM4 0x01000000 /* uVax ROM 4 ok */
! 285: #define PUDR_UVAX 0x00800000 /* uVax passes self test */
! 286: #define PUDR_BI 0x00400000 /* BIIC and BCI3 chips ok */
! 287: #define PUDR_TMR 0x00200000 /* interval timer ok */
! 288: #define PUDR_IRQ 0x00100000 /* no IRQ lines stuck */
! 289: #define PUDR_NI 0x00080000 /* Ethernet ctlr ok */
! 290: #define PUDR_TK50 0x00040000 /* tk50 present */
! 291: #define PUDR_PRES 0x00001000 /* tk50 present (again?!) */
! 292: #define PUDR_UVINT 0x00000800 /* uVax-to-80186 intr logic ok */
! 293: #define PUDR_BUSHD 0x00000400 /* no bus hold errors */
! 294: #define PUDR_II32 0x00000200 /* II32 transceivers ok */
! 295: #define PUDR_MPSC 0x00000100 /* MPSC logic ok */
! 296: #define PUDR_GAP 0x00000080 /* gap-detect logic ok */
! 297: #define PUDR_MISC 0x00000040 /* misc. registers ok */
! 298: #define PUDR_UNEXP 0x00000020 /* unexpected interrupt trapped */
! 299: #define PUDR_80186 0x00000010 /* 80186 ok */
! 300: #define PUDR_PATCH2 0x00000008 /* patch logic ok (again) */
! 301: #define PUDR_8RAM 0x00000004 /* 80186 RAM ok */
! 302: #define PUDR_8ROM2 0x00000002 /* 80186 ROM1 ok */
! 303: #define PUDR_8ROM1 0x00000001 /* 80186 ROM2 ok */
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