Annotation of sys/arch/sparc64/sparc64/cache.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cache.h,v 1.5 2007/01/12 22:09:08 kettenis Exp $ */
2: /* $NetBSD: cache.h,v 1.3 2000/08/01 00:28:02 eeh Exp $ */
3:
4: /*
5: * Copyright (c) 1996
6: * The President and Fellows of Harvard College. All rights reserved.
7: * Copyright (c) 1992, 1993
8: * The Regents of the University of California. All rights reserved.
9: *
10: * This software was developed by the Computer Systems Engineering group
11: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
12: * contributed to Berkeley.
13: *
14: * Redistribution and use in source and binary forms, with or without
15: * modification, are permitted provided that the following conditions
16: * are met:
17: * 1. Redistributions of source code must retain the above copyright
18: * notice, this list of conditions and the following disclaimer.
19: * 2. Redistributions in binary form must reproduce the above copyright
20: * notice, this list of conditions and the following disclaimer in the
21: * documentation and/or other materials provided with the distribution.
22: * 3. All advertising materials mentioning features or use of this software
23: * must display the following acknowledgement:
24: * This product includes software developed by Aaron Brown and
25: * Harvard University.
26: * This product includes software developed by the University of
27: * California, Berkeley and its contributors.
28: * 4. Neither the name of the University nor the names of its contributors
29: * may be used to endorse or promote products derived from this software
30: * without specific prior written permission.
31: *
32: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
33: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
36: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
40: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
42: * SUCH DAMAGE.
43: *
44: * @(#)cache.h 8.1 (Berkeley) 6/11/93
45: */
46:
47: enum vactype { VAC_NONE, VAC_WRITETHROUGH, VAC_WRITEBACK };
48:
49: extern enum vactype vactype; /* XXX move into cacheinfo struct */
50:
51: /*
52: * Cache tags can be written in control space, and must be set to 0
53: * (or invalid anyway) before turning on the cache. The tags are
54: * addressed as an array of 32-bit structures of the form:
55: *
56: * struct cache_tag {
57: * u_int :7, (unused; must be zero)
58: * ct_cid:3, (context ID)
59: * ct_w:1, (write flag from PTE)
60: * ct_s:1, (supervisor flag from PTE)
61: * ct_v:1, (set => cache entry is valid)
62: * :3, (unused; must be zero)
63: * ct_tid:14, (cache tag ID)
64: * :2; (unused; must be zero)
65: * };
66: *
67: * The SPARCstation 1 cache sees virtual addresses as:
68: *
69: * struct cache_va {
70: * u_int :2, (unused; probably copies of va_tid<13>)
71: * cva_tid:14, (tag ID)
72: * cva_line:12, (cache line number)
73: * cva_byte:4; (byte in cache line)
74: * };
75: *
76: * (The SS2 cache is similar but has half as many lines, each twice as long.)
77: *
78: * Note that, because the 12-bit line ID is `wider' than the page offset,
79: * it is possible to have one page map to two different cache lines.
80: * This can happen whenever two different physical pages have the same bits
81: * in the part of the virtual address that overlaps the cache line ID, i.e.,
82: * bits <15:12>. In order to prevent cache duplication, we have to
83: * make sure that no one page has more than one virtual address where
84: * (va1 & 0xf000) != (va2 & 0xf000). (The cache hardware turns off ct_v
85: * when a cache miss occurs on a write, i.e., if va1 is in the cache and
86: * va2 is not, and you write to va2, va1 goes out of the cache. If va1
87: * is in the cache and va2 is not, reading va2 also causes va1 to become
88: * uncached, and the [same] data is then read from main memory into the
89: * cache.)
90: *
91: * The other alternative, of course, is to disable caching of aliased
92: * pages. (In a few cases this might be faster anyway, but we do it
93: * only when forced.)
94: *
95: * The Sun4, since it has an 8K pagesize instead of 4K, needs to check
96: * bits that are one position higher.
97: */
98:
99: /*
100: * The spitfire has a 16K two-way set associative level-1 I$ and a separate
101: * 16K level-1 D$. The I$ can be invalidated using the FLUSH instructions,
102: * so we don't really need to worry about it much. The D$ is 16K write-through
103: * direct mapped virtually addressed cache with two 16-byte sub-blocks per line.
104: * The E$ is a 512KB-4MB direct mapped physically indexed physically tagged cache.
105: * Since the level-1 caches are write-through, they don't need flushing and can be
106: * invalidated directly.
107: *
108: * The spitfire sees virtual addresses as:
109: *
110: * struct cache_va {
111: * u_int64_t :22, (unused; we only have 40-bit addresses)
112: * cva_tag:28, (tag ID)
113: * cva_line:9, (cache line number)
114: * cva_byte:5; (byte within line)
115: * };
116: *
117: * Since there is one bit of overlap between the page offset and the line index,
118: * all we need to do is make sure that bit 14 of the va remains constant and we have
119: * no aliasing problems.
120: *
121: * Let me try again. Page size is 8K, cache size is 16K so if (va1&0x3fff != va2&0x3fff)
122: * we have a problem. Bit 14 *must* be the same for all mappings of a page to be cacheable
123: * in the D$. (The I$ is 16K 2-way associative--each bank is 8K. No conflict there.)
124: */
125:
126: /* Some more well-known values: */
127: #define CACHE_ALIAS_MASK 0x7fff
128: #define CACHE_ALIAS_BITS 0x4000
129:
130: /*
131: * True iff a1 and a2 are `bad' aliases (will cause cache duplication).
132: */
133: #define BADALIAS(a1, a2) (((int)(a1) ^ (int)(a2)) & CACHE_ALIAS_BITS)
134:
135: /*
136: * Routines for dealing with the cache.
137: */
138: void cache_enable(void); /* turn it on */
139: int cache_flush_page(paddr_t); /* flush page from E$ */
140: int cache_flush(vaddr_t, vsize_t); /* flush region */
141:
142: /* The following are for D$ flushes and are in locore.s */
143: #define dcache_flush_page(pa) cacheinfo.c_dcache_flush_page(pa)
144: void us_dcache_flush_page(paddr_t); /* flush page from D$ */
145: void us3_dcache_flush_page(paddr_t); /* flush page from D$ */
146:
147: /* The following flush a range from the D$ and I$ but not E$. */
148: void cache_flush_virt(vaddr_t, vsize_t);
149: void cache_flush_phys(paddr_t, psize_t, int);
150:
151: /*
152: * Cache control information.
153: */
154: struct cacheinfo {
155: void (*c_dcache_flush_page)(paddr_t);
156:
157: int c_totalsize; /* total size, in bytes */
158: /* if split, MAX(icache,dcache) */
159: int c_enabled; /* true => cache is enabled */
160: int c_hwflush; /* true => have hardware flush */
161: int c_linesize; /* line size, in bytes */
162: int c_l2linesize; /* log2(linesize) */
163: int c_physical; /* true => cache is physical */
164: int c_split; /* true => cache is split */
165: int ic_totalsize; /* instruction cache */
166: int ic_enabled;
167: int ic_linesize;
168: int ic_l2linesize;
169: int dc_totalsize; /* data cache */
170: int dc_enabled;
171: int dc_linesize;
172: int dc_l2linesize;
173: int ec_totalsize; /* external cache info */
174: int ec_enabled;
175: int ec_linesize;
176: int ec_l2linesize;
177: };
178: extern struct cacheinfo cacheinfo;
179:
180: /*
181: * Cache control statistics.
182: */
183: struct cachestats {
184: int cs_npgflush; /* # page flushes */
185: int cs_nraflush; /* # range flushes */
186: #ifdef notyet
187: int cs_ra[65]; /* pages/range */
188: #endif
189: };
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