Annotation of sys/arch/sparc64/include/ctlreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ctlreg.h,v 1.11 2007/03/13 19:27:50 kettenis Exp $ */
2: /* $NetBSD: ctlreg.h,v 1.28 2001/08/06 23:55:34 eeh Exp $ */
3:
4: /*
5: * Copyright (c) 1996-2001 Eduardo Horvath
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: *
13: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
14: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
17: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23: * SUCH DAMAGE.
24: *
25: */
26: /*
27: * Copyright (c) 2001 Jake Burkholder.
28: * All rights reserved.
29: *
30: * Redistribution and use in source and binary forms, with or without
31: * modification, are permitted provided that the following conditions
32: * are met:
33: * 1. Redistributions of source code must retain the above copyright
34: * notice, this list of conditions and the following disclaimer.
35: * 2. Redistributions in binary form must reproduce the above copyright
36: * notice, this list of conditions and the following disclaimer in the
37: * documentation and/or other materials provided with the distribution.
38: *
39: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
40: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
42: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
43: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
44: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
45: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
46: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
47: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
48: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
49: * SUCH DAMAGE.
50: */
51:
52: #ifndef _SPARC64_CTLREG_
53: #define _SPARC64_CTLREG_
54:
55: /*
56: * Sun 4u control registers. (includes address space definitions
57: * and some registers in control space).
58: */
59:
60: /*
61: * membar operand macros for use in other macros when # is a special
62: * character. Keep these in sync with what the hardware expects.
63: */
64: #define C_Lookaside (0)
65: #define C_MemIssue (1)
66: #define C_Sync (2)
67: #define M_LoadLoad (0)
68: #define M_StoreLoad (1)
69: #define M_LoadStore (2)
70: #define M_StoreStore (3)
71:
72: #define CMASK_SHIFT (4)
73: #define MMASK_SHIFT (0)
74:
75: #define CMASK_GEN(bit) ((1 << (bit)) << CMASK_SHIFT)
76: #define MMASK_GEN(bit) ((1 << (bit)) << MMASK_SHIFT)
77:
78: /*
79: * The Alternate address spaces.
80: *
81: * 0x00-0x7f are privileged
82: * 0x80-0xff can be used by users
83: */
84:
85: #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */
86:
87: #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */
88: #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */
89:
90: #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */
91: #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */
92:
93: #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */
94: #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */
95:
96: #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */
97: #define ASI_AS_IF_USER_SECONDARY_LITTIE 0x19 /* [4u] secondary user address space, little endian */
98:
99: #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */
100: #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */
101:
102: #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */
103: #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */
104:
105: #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */
106: #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */
107: #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */
108: #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */
109:
110: #define ASI_DCACHE_INVALIDATE 0x42 /* [III] invalidate D-cache */
111: #define ASI_DCACHE_UTAG 0x43 /* [III] diagnostic access to D-cache micro tag */
112: #define ASI_DCACHE_SNOOP_TAG 0x44 /* [III] diagnostic access to D-cache snoop tag RAM */
113:
114: #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */
115:
116: #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */
117: #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */
118:
119: #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */
120: #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */
121: #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */
122: #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */
123: #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */
124: #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */
125:
126: #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */
127: #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */
128: #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */
129: #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */
130: #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */
131: #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */
132:
133: #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */
134: #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */
135:
136: #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */
137: #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */
138:
139: #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */
140: #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */
141:
142: #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */
143: #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */
144:
145: #define ASI_PRIMARY 0x80 /* [4u] primary address space */
146: #define ASI_SECONDARY 0x81 /* [4u] secondary address space */
147: #define ASI_PRIMARY_NOFAULT 0x82 /* [4u] primary address space, no fault */
148: #define ASI_SECONDARY_NOFAULT 0x83 /* [4u] secondary address space, no fault */
149:
150: #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */
151: #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */
152: #define ASI_PRIMARY_NOFAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */
153: #define ASI_SECONDARY_NOFAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */
154:
155: #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */
156: #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */
157: #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */
158: #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */
159: #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */
160: #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */
161:
162: #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */
163: #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */
164: #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */
165: #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */
166: #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */
167: #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */
168:
169: #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */
170: #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */
171: #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */
172: #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */
173:
174: #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */
175: #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */
176: #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */
177: #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */
178:
179: #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */
180: #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */
181: #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */
182: #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */
183: #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */
184: #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */
185:
186:
187: /*
188: * These are the shorter names used by Solaris
189: */
190:
191: #define ASI_N ASI_NUCLEUS
192: #define ASI_NL ASI_NUCLEUS_LITTLE
193: #define ASI_AIUP ASI_AS_IF_USER_PRIMARY
194: #define ASI_AIUS ASI_AS_IF_USER_SECONDARY
195: #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE
196: #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE
197: #define ASI_P ASI_PRIMARY
198: #define ASI_S ASI_SECONDARY
199: #define ASI_PNF ASI_PRIMARY_NOFAULT
200: #define ASI_SNF ASI_SECONDARY_NOFAULT
201: #define ASI_PL ASI_PRIMARY_LITTLE
202: #define ASI_SL ASI_SECONDARY_LITTLE
203: #define ASI_PNFL ASI_PRIMARY_NOFAULT_LITTLE
204: #define ASI_SNFL ASI_SECONDARY_NOFAULT_LITTLE
205: #define ASI_FL8_P ASI_FL8_PRIMARY
206: #define ASI_FL8_S ASI_FL8_SECONDARY
207: #define ASI_FL16_P ASI_FL16_PRIMARY
208: #define ASI_FL16_S ASI_FL16_SECONDARY
209: #define ASI_FL8_PL ASI_FL8_PRIMARY_LITTLE
210: #define ASI_FL8_SL ASI_FL8_SECONDARY_LITTLE
211: #define ASI_FL16_PL ASI_FL16_PRIMARY_LITTLE
212: #define ASI_FL16_SL ASI_FL16_SECONDARY_LITTLE
213: #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY
214: #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
215: #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY
216: #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
217: #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY
218: #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY
219: #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY
220: #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY
221: #define ASI_BLK_P ASI_BLOCK_PRIMARY
222: #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE
223: #define ASI_BLK_S ASI_BLOCK_SECONDARY
224: #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE
225:
226: /* Alternative spellings */
227: #define ASI_PRIMARY_NO_FAULT ASI_PRIMARY_NOFAULT
228: #define ASI_PRIMARY_NO_FAULT_LITTLE ASI_PRIMARY_NOFAULT_LITTLE
229: #define ASI_SECONDARY_NO_FAULT ASI_SECONDARY_NOFAULT
230: #define ASI_SECONDARY_NO_FAULT_LITTLE ASI_SECONDARY_NOFAULT_LITTLE
231:
232: #define PHYS_ASI(x) (((x) | 0x09) == 0x1d)
233: #define LITTLE_ASI(x) ((x) & ASI_LITTLE)
234:
235: /*
236: * %tick: cpu cycle counter
237: */
238: #define TICK_NPT 0x8000000000000000 /* trap on non priv access */
239: #define TICK_TICKS 0x7fffffffffffffff /* counter bits */
240:
241: /*
242: * The following are 4u control registers
243: */
244:
245:
246: /* Get the CPU's UPAID */
247: #define UPA_CR_MID(x) (((x)>>17)&0x1f)
248: #define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG))
249:
250: /*
251: * [4u] MMU and Cache Control Register (MCCR)
252: * use ASI = 0x45
253: */
254: #define ASI_MCCR ASI_LSU_CONTROL_REGISTER
255: #define MCCR 0x00
256:
257: /* MCCR Bits and their meanings */
258: #define MCCR_DMMU_EN 0x08
259: #define MCCR_IMMU_EN 0x04
260: #define MCCR_DCACHE_EN 0x02
261: #define MCCR_ICACHE_EN 0x01
262:
263:
264: /*
265: * MMU control registers
266: */
267:
268: /* Choose an MMU */
269: #define ASI_DMMU 0x58
270: #define ASI_IMMU 0x50
271:
272: /* Other assorted MMU ASIs */
273: #define ASI_IMMU_8KPTR 0x51
274: #define ASI_IMMU_64KPTR 0x52
275: #define ASI_IMMU_DATA_IN 0x54
276: #define ASI_IMMU_TLB_DATA 0x55
277: #define ASI_IMMU_TLB_TAG 0x56
278: #define ASI_DMMU_8KPTR 0x59
279: #define ASI_DMMU_64KPTR 0x5a
280: #define ASI_DMMU_DATA_IN 0x5c
281: #define ASI_DMMU_TLB_DATA 0x5d
282: #define ASI_DMMU_TLB_TAG 0x5e
283:
284: /*
285: * The following are the control registers
286: * They work on both MMUs unless noted.
287: * III = cheetah only
288: *
289: * Register contents are defined later on individual registers.
290: */
291: #define TSB_TAG_TARGET 0x0
292: #define TLB_DATA_IN 0x0
293: #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */
294: #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */
295: #define SFSR 0x18
296: #define SFAR 0x20 /* fault address -- DMMU only */
297: #define TSB 0x28
298: #define TLB_TAG_ACCESS 0x30
299: #define VIRTUAL_WATCHPOINT 0x38
300: #define PHYSICAL_WATCHPOINT 0x40
301: #define TSB_PEXT 0x48 /* III primary ext */
302: #define TSB_SEXT 0x50 /* III 2ndary ext -- DMMU only */
303: #define TSB_NEXT 0x58 /* III nucleus ext */
304:
305: /* Tag Target bits */
306: #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL
307: #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK)
308: #define TAG_TARGET_CONTEXT(x) ((x)>>48)
309: #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK))
310:
311: /* SFSR bits for both D_SFSR and I_SFSR */
312: #define SFSR_NF 0x1000000 /* Non-faulting load */
313: #define SFSR_ASI(x) ((x)>>16)
314: #define SFSR_TM 0x0008000 /* TLB miss */
315: #define SFSR_FT_VA_OOR_2 0x0002000 /* IMMU: jumpl or return to unsupportd VA */
316: #define SFSR_FT_VA_OOR_1 0x0001000 /* fault at unsupported VA */
317: #define SFSR_FT_NFO 0x0000800 /* DMMU: Access to page marked NFO */
318: #define SFSR_ILL_ASI 0x0000400 /* DMMU: Illegal (unsupported) ASI */
319: #define SFSR_FT_IO_ATOMIC 0x0000200 /* DMMU: Atomic access to noncacheable page */
320: #define SFSR_FT_ILL_NF 0x0000100 /* DMMU: NF load or flush to page marked E (has side effects) */
321: #define SFSR_FT_PRIV 0x0000080 /* Privilege violation */
322: #define SFSR_FT_E 0x0000040 /* DMUU: value of E bit associated address */
323: #define SFSR_CTXT(x) (((x)>>4)&0x3)
324: #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00)
325: #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01)
326: #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02)
327: #define SFSR_PRIV 0x0000008 /* value of PSTATE.PRIV for faulting access */
328: #define SFSR_W 0x0000004 /* DMMU: attempted write */
329: #define SFSR_OW 0x0000002 /* Overwrite; prev fault was still valid */
330: #define SFSR_FV 0x0000001 /* Fault is valid */
331: #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV)
332:
333: #define SFSR_BITS "\20\31NF\20TM\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV"
334:
335: /* ASFR bits */
336: #define ASFR_ME 0x100000000LL
337: #define ASFR_PRIV 0x080000000LL
338: #define ASFR_ISAP 0x040000000LL
339: #define ASFR_ETP 0x020000000LL
340: #define ASFR_IVUE 0x010000000LL
341: #define ASFR_TO 0x008000000LL
342: #define ASFR_BERR 0x004000000LL
343: #define ASFR_LDP 0x002000000LL
344: #define ASFR_CP 0x001000000LL
345: #define ASFR_WP 0x000800000LL
346: #define ASFR_EDP 0x000400000LL
347: #define ASFR_UE 0x000200000LL
348: #define ASFR_CE 0x000100000LL
349: #define ASFR_ETS 0x0000f0000LL
350: #define ASFT_P_SYND 0x00000ffffLL
351:
352: #define AFSR_BITS "\20" \
353: "\20ME\37PRIV\36ISAP\35ETP\34IVUE\33TO\32BERR\31LDP\30CP\27WP\26EDP" \
354: "\25UE\24CE"
355:
356: /*
357: * Here's the spitfire TSB control register bits.
358: *
359: * Each TSB entry is 16-bytes wide. The TSB must be size aligned
360: */
361: #define TSB_SIZE_512 0x0 /* 8kB, etc. */
362: #define TSB_SIZE_1K 0x01
363: #define TSB_SIZE_2K 0x02
364: #define TSB_SIZE_4K 0x03
365: #define TSB_SIZE_8K 0x04
366: #define TSB_SIZE_16K 0x05
367: #define TSB_SIZE_32K 0x06
368: #define TSB_SIZE_64K 0x07
369: #define TSB_SPLIT 0x1000
370: #define TSB_BASE 0xffffffffffffe000
371:
372: /* TLB Tag Access bits */
373: #define TLB_TAG_ACCESS_VA 0xffffffffffffe000
374: #define TLB_TAG_ACCESS_CTX 0x0000000000001fff
375:
376: /*
377: * TLB demap registers. TTEs are defined in v9pte.h
378: *
379: * Use the address space to select between IMMU and DMMU.
380: * The address of the register selects which context register
381: * to read the ASI from.
382: *
383: * The data stored in the register is interpreted as the VA to
384: * use. The DEMAP_CTX_<> registers ignore the address and demap the
385: * entire ASI.
386: *
387: */
388: #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */
389: #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */
390:
391: #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */
392: #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */
393: #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */
394: #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */
395: #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */
396: #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */
397:
398: /*
399: * Interrupt registers. This really gets hairy.
400: */
401:
402: /* IRSR -- Interrupt Receive Status Ragister */
403: #define ASI_IRSR 0x49
404: #define IRSR 0x00
405: #define IRSR_BUSY 0x020
406: #define IRSR_MID(x) (x&0x1f)
407:
408: /* IRDR -- Interrupt Receive Data Registers */
409: #define ASI_IRDR 0x7f
410: #define IRDR_0H 0x40
411: #define IRDR_0L 0x48 /* unimplemented */
412: #define IRDR_1H 0x50
413: #define IRDR_1L 0x58 /* unimplemented */
414: #define IRDR_2H 0x60
415: #define IRDR_2L 0x68 /* unimplemented */
416: #define IRDR_3H 0x70 /* unimplemented */
417: #define IRDR_3L 0x78 /* unimplemented */
418:
419: /* SOFTINT ASRs */
420: #define SET_SOFTINT %asr20 /* Sets these bits */
421: #define CLEAR_SOFTINT %asr21 /* Clears these bits */
422: #define SOFTINT %asr22 /* Reads the register */
423: #define TICK_CMPR %asr23
424:
425: #define TICK_INT 0x01 /* level-14 clock tick */
426: #define SOFTINT1 (0x1<<1)
427: #define SOFTINT2 (0x1<<2)
428: #define SOFTINT3 (0x1<<3)
429: #define SOFTINT4 (0x1<<4)
430: #define SOFTINT5 (0x1<<5)
431: #define SOFTINT6 (0x1<<6)
432: #define SOFTINT7 (0x1<<7)
433: #define SOFTINT8 (0x1<<8)
434: #define SOFTINT9 (0x1<<9)
435: #define SOFTINT10 (0x1<<10)
436: #define SOFTINT11 (0x1<<11)
437: #define SOFTINT12 (0x1<<12)
438: #define SOFTINT13 (0x1<<13)
439: #define SOFTINT14 (0x1<<14)
440: #define SOFTINT15 (0x1<<15)
441:
442: /* Interrupt Dispatch -- usually reserved for cross-calls */
443: #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */
444: #define IDSR 0x00
445: #define IDSR_NACK 0x02
446: #define IDSR_BUSY 0x01
447:
448: #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */
449: #define IDCR(x) (((x)<<14)&0x70) /* Store anything to this address to dispatch crosscall to CPU (x) */
450: #define IDDR_0H 0x40 /* Store data to send in these regs */
451: #define IDDR_0L 0x48 /* unimplemented */
452: #define IDDR_1H 0x50
453: #define IDDR_1L 0x58 /* unimplemented */
454: #define IDDR_2H 0x60
455: #define IDDR_2L 0x68 /* unimplemented */
456: #define IDDR_3H 0x70 /* unimplemented */
457: #define IDDR_3L 0x78 /* unimplemented */
458:
459: /*
460: * Error registers
461: */
462:
463: /* Since we won't try to fix async errs, we don't care about the bits in the regs */
464: #define ASI_AFAR 0x4d /* Asynchronous fault address register */
465: #define AFAR 0x00
466: #define ASI_AFSR 0x4c /* Asynchronous fault status register */
467: #define AFSR 0x00
468:
469: #define ASI_P_EER 0x4b /* Error enable register */
470: #define P_EER 0x00
471: #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */
472: #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */
473: #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */
474:
475: #define ASI_DATAPATH_READ 0x7f /* Read the regs */
476: #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */
477: #define P_DPER_0 0x00 /* Datapath err reg 0 */
478: #define P_DPER_1 0x18 /* Datapath err reg 1 */
479: #define P_DCR_0 0x20 /* Datapath control reg 0 */
480: #define P_DCR_1 0x38 /* Datapath control reg 0 */
481:
482:
483: /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */
484:
485: #ifndef _LOCORE
486: /*
487: * GCC __asm constructs for doing assembly stuff.
488: */
489:
490: /*
491: * ``Routines'' to load and store from/to alternate address space.
492: * The location can be a variable, the asi value (address space indicator)
493: * must be a constant.
494: *
495: * N.B.: You can put as many special functions here as you like, since
496: * they cost no kernel space or time if they are not used.
497: *
498: * These were static inline functions, but gcc screws up the constraints
499: * on the address space identifiers (the "n"umeric value part) because
500: * it inlines too late, so we have to use the funny valued-macro syntax.
501: */
502:
503: /*
504: * Apparently the definition of bypass ASIs is that they all use the
505: * D$ so we need to flush the D$ to make sure we don't get data pollution.
506: */
507:
508: extern __inline u_int32_t sparc_cas(u_int32_t *, u_int32_t, u_int32_t);
509: extern __inline u_int32_t
510: sparc_cas(u_int32_t *rs1, u_int32_t rs2, u_int32_t rd)
511: {
512: __asm __volatile("casa [%1] ASI_PRIMARY, %2, %0"
513: : "+r" (rd)
514: : "r" (rs1), "r" (rs2)
515: : "memory" );
516: return (rd);
517: }
518:
519: extern __inline u_int64_t sparc_casx(u_int64_t *, u_int64_t, u_int64_t);
520: extern __inline u_int64_t
521: sparc_casx(u_int64_t *rs1, u_int64_t rs2, u_int64_t rd)
522: {
523: __asm __volatile("casxa [%1] ASI_PRIMARY, %3, %0"
524: : "+r" (rd)
525: : "r" (rs1), "r" (rs2)
526: : "memory" );
527: return (rd);
528: }
529:
530: #define sparc_membar(mask) do { \
531: if (mask) \
532: __asm __volatile("membar %0" : : "n" (mask) : "memory");\
533: else \
534: __asm __volatile("" : : : "memory"); \
535: } while(0)
536:
537: #define membar sparc_membar
538: #define Lookaside CMASK_GEN(C_Lookaside)
539: #define MemIssue CMASK_GEN(C_MemIssue)
540: #define Sync CMASK_GEN(C_Sync)
541: #define LoadLoad MMASK_GEN(M_LoadLoad)
542: #define StoreLoad MMASK_GEN(M_StoreLoad)
543: #define LoadStore MMASK_GEN(M_LoadStore)
544: #define StoreStore MMASK_GEN(M_StoreStore)
545:
546: #define sparc_wr(name, val, xor) \
547: do { \
548: if (__builtin_constant_p(xor)) \
549: __asm __volatile("wr %%g0, %0, %%" #name \
550: : : "rI" ((val) ^ (xor)) : "%g0"); \
551: else \
552: __asm __volatile("wr %0, %1, %%" #name \
553: : : "r" (val), "rI" (xor) : "%g0"); \
554: } while(0)
555:
556: #define sparc_wrpr(name, val, xor) \
557: do { \
558: if (__builtin_constant_p(xor)) \
559: __asm __volatile("wrpr %%g0, %0, %%" #name \
560: : : "rI" ((val) ^ (xor)) : "%g0"); \
561: else \
562: __asm __volatile("wrpr %0, %1, %%" #name \
563: : : "r" (val), "rI" (xor) : "%g0"); \
564: } while(0)
565:
566:
567: #define sparc_rd(name) sparc_rd_ ## name()
568: #define GEN_RD(name) \
569: extern __inline u_int64_t sparc_rd_ ## name(void); \
570: extern __inline u_int64_t \
571: sparc_rd_ ## name() \
572: { \
573: u_int64_t r; \
574: __asm __volatile("rd %%" #name ", %0" : \
575: "=r" (r) : : "%g0"); \
576: return (r); \
577: }
578:
579: #define sparc_rdpr(name) sparc_rdpr_ ## name()
580: #define GEN_RDPR(name) \
581: extern __inline u_int64_t sparc_rdpr_ ## name(void); \
582: extern __inline u_int64_t \
583: sparc_rdpr_ ## name() \
584: { \
585: u_int64_t r; \
586: __asm __volatile("rdpr %%" #name ", %0" : \
587: "=r" (r) : : "%g0"); \
588: return (r); \
589: }
590:
591: GEN_RD(asi);
592: GEN_RD(asr22);
593: GEN_RDPR(cwp);
594: GEN_RDPR(tick);
595: GEN_RDPR(pstate);
596: GEN_RDPR(pil);
597: GEN_RDPR(ver);
598: /*
599: * Before adding GEN_RDPRs for other registers, see Errata 50 (E.g,. in
600: * the US-IIi manual) regarding tstate, pc and npc reads.
601: */
602:
603: /* Generate ld*a/st*a functions for non-constant ASI's. */
604: #define LDNC_GEN(tp, o) \
605: extern __inline tp o ## _asi(paddr_t); \
606: extern __inline tp \
607: o ## _asi(paddr_t va) \
608: { \
609: tp r; \
610: __asm __volatile( \
611: #o " [%1] %%asi, %0" \
612: : "=r" (r) \
613: : "r" ((volatile tp *)va) \
614: : "%g0"); \
615: return (r); \
616: } \
617: extern __inline tp o ## _nc(paddr_t, int); \
618: extern __inline tp \
619: o ## _nc(paddr_t va, int asi) \
620: { \
621: sparc_wr(asi, asi, 0); \
622: return (o ## _asi(va)); \
623: }
624:
625: LDNC_GEN(u_char, lduba);
626: LDNC_GEN(u_short, lduha);
627: LDNC_GEN(u_int, lduwa);
628: LDNC_GEN(u_int64_t, ldxa);
629:
630: LDNC_GEN(int, lda);
631:
632: #define LDC_GEN(va, asi, op, opa, type) ({ \
633: type __r ## op ## type; \
634: if(asi == ASI_PRIMARY || \
635: (sizeof(type) == 1 && asi == ASI_PRIMARY_LITTLE)) \
636: __r ## op ## type = *((volatile type *)va); \
637: else \
638: __asm __volatile(#opa " [%1] " #asi ", %0" \
639: : "=r" (__r ## op ## type) \
640: : "r" ((volatile type *)va) \
641: : "%g0"); \
642: __r ## op ## type; \
643: })
644:
645: #ifdef __OPTIMIZE__
646: #define LD_GENERIC(va, asi, op, type) (__builtin_constant_p(asi) ? \
647: LDC_GEN((va), asi, op, op ## a, type) : op ## a_nc((va), asi))
648: #else /* __OPTIMIZE */
649: #define LD_GENERIC(va, asi, op, type) (op ## a_nc((va), asi))
650: #endif /* __OPTIMIZE__ */
651:
652: #define lduba(va, asi) LD_GENERIC(va, asi, ldub, u_int8_t)
653: #define lduha(va, asi) LD_GENERIC(va, asi, lduh, u_int16_t)
654: #define lduwa(va, asi) LD_GENERIC(va, asi, lduw, u_int32_t)
655: #define ldxa(va, asi) LD_GENERIC(va, asi, ldx, u_int64_t)
656:
657: #define STNC_GEN(tp, o) \
658: extern __inline void o ## _asi(paddr_t, tp); \
659: extern __inline void \
660: o ## _asi(paddr_t va, tp val) \
661: { \
662: __asm __volatile( \
663: #o " %0, [%1] %%asi" \
664: : \
665: : "r" (val), "r" ((volatile tp *)va) \
666: : "memory"); \
667: } \
668: extern __inline void o ## _nc(paddr_t, int, tp); \
669: extern __inline void \
670: o ## _nc(paddr_t va, int asi, tp val) \
671: { \
672: sparc_wr(asi, asi, 0); \
673: o ## _asi(va, val); \
674: }
675:
676: STNC_GEN(u_int8_t, stba);
677: STNC_GEN(u_int16_t, stha);
678: STNC_GEN(u_int32_t, stwa);
679: STNC_GEN(u_int64_t, stxa);
680:
681: STNC_GEN(u_int, sta);
682:
683: #define STC_GEN(va, asi, val, op, opa, type) ({ \
684: if(asi == ASI_PRIMARY || \
685: (sizeof(type) == 1 && asi == ASI_PRIMARY_LITTLE)) \
686: *((volatile type *)va) = val; \
687: else \
688: __asm __volatile(#opa " %0, [%1] " #asi \
689: : : "r" (val), "r" ((volatile type *)va) \
690: : "memory"); \
691: })
692:
693: #ifdef __OPTIMIZE__
694: #define ST_GENERIC(va, asi, val, op, type) (__builtin_constant_p(asi) ? \
695: STC_GEN((va), (asi), (val), op, op ## a, type) : \
696: op ## a_nc((va), asi, (val)))
697: #else /* __OPTIMIZE__ */
698: #define ST_GENERIC(va, asi, val, op, type) (op ## a_nc((va), asi, (val)))
699: #endif /* __OPTIMIZE__ */
700:
701: #define stba(va, asi, val) ST_GENERIC(va, asi, val, stb, u_int8_t)
702: #define stha(va, asi, val) ST_GENERIC(va, asi, val, sth, u_int16_t)
703: #define stwa(va, asi, val) ST_GENERIC(va, asi, val, stw, u_int32_t)
704: #define stxa(va, asi, val) ST_GENERIC(va, asi, val, stx, u_int64_t)
705:
706:
707: extern __inline void asi_set(int);
708: extern __inline
709: void asi_set(int asi)
710: {
711: sparc_wr(asi, asi, 0);
712: }
713:
714: extern __inline u_int8_t asi_get(void);
715: extern __inline
716: u_int8_t asi_get()
717: {
718: return sparc_rd(asi);
719: }
720:
721: /* flush address from instruction cache */
722: extern __inline void flush(void *);
723: extern __inline
724: void flush(void *p)
725: {
726: __asm __volatile("flush %0"
727: : : "r" (p)
728: : "memory");
729: }
730:
731: /* read 64-bit %tick register */
732: #define tick() (sparc_rdpr(tick) & TICK_TICKS)
733:
734: extern void next_tick(long);
735:
736: #endif /* _LOCORE */
737: #endif /* _SPARC64_CTLREG_ */
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