Annotation of sys/arch/sparc64/include/cpu.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cpu.h,v 1.40 2007/05/14 21:38:08 kettenis Exp $ */
2: /* $NetBSD: cpu.h,v 1.28 2001/06/14 22:56:58 thorpej Exp $ */
3:
4: /*
5: * Copyright (c) 1992, 1993
6: * The Regents of the University of California. All rights reserved.
7: *
8: * This software was developed by the Computer Systems Engineering group
9: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10: * contributed to Berkeley.
11: *
12: * All advertising materials mentioning features or use of this software
13: * must display the following acknowledgement:
14: * This product includes software developed by the University of
15: * California, Lawrence Berkeley Laboratory.
16: *
17: * Redistribution and use in source and binary forms, with or without
18: * modification, are permitted provided that the following conditions
19: * are met:
20: * 1. Redistributions of source code must retain the above copyright
21: * notice, this list of conditions and the following disclaimer.
22: * 2. Redistributions in binary form must reproduce the above copyright
23: * notice, this list of conditions and the following disclaimer in the
24: * documentation and/or other materials provided with the distribution.
25: * 3. Neither the name of the University nor the names of its contributors
26: * may be used to endorse or promote products derived from this software
27: * without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39: * SUCH DAMAGE.
40: *
41: * @(#)cpu.h 8.4 (Berkeley) 1/5/94
42: */
43:
44: #ifndef _CPU_H_
45: #define _CPU_H_
46:
47: /*
48: * CTL_MACHDEP definitions.
49: */
50: #define CPU_LED_BLINK 2 /* int: blink leds? */
51: #define CPU_ALLOWAPERTURE 3 /* allow xf86 operations */
52: #define CPU_CPUTYPE 4 /* cpu type */
53: #define CPU_CECCERRORS 5 /* Correctable ECC errors */
54: #define CPU_CECCLAST 6 /* Correctable ECC last fault addr */
55: #define CPU_KBDRESET 7 /* soft reset via keyboard */
56: #define CPU_MAXID 8 /* number of valid machdep ids */
57:
58: #define CTL_MACHDEP_NAMES { \
59: { 0, 0 }, \
60: { 0, 0 }, \
61: { "led_blink", CTLTYPE_INT }, \
62: { "allowaperture", CTLTYPE_INT }, \
63: { "cputype", CTLTYPE_INT }, \
64: { "ceccerrs", CTLTYPE_INT }, \
65: { "cecclast", CTLTYPE_QUAD }, \
66: { "kbdreset", CTLTYPE_INT }, \
67: }
68:
69: #ifdef _KERNEL
70: /*
71: * Exported definitions unique to SPARC cpu support.
72: */
73:
74: #include <machine/ctlreg.h>
75: #include <machine/psl.h>
76: #include <machine/reg.h>
77: #include <machine/intr.h>
78:
79: #include <sys/sched.h>
80:
81: /*
82: * The cpu_info structure is part of a 64KB structure mapped both the kernel
83: * pmap and a single locked TTE a CPUINFO_VA for that particular processor.
84: * Each processor's cpu_info is accessible at CPUINFO_VA only for that
85: * processor. Other processors can access that through an additional mapping
86: * in the kernel pmap.
87: *
88: * The 64KB page contains:
89: *
90: * cpu_info
91: * interrupt stack (all remaining space)
92: * idle PCB
93: * idle stack (STACKSPACE - sizeof(PCB))
94: * 32KB TSB
95: */
96:
97: struct cpu_info {
98: /* Most important fields first */
99: struct proc *ci_curproc;
100: struct pcb *ci_cpcb; /* also initial stack */
101: struct cpu_info *ci_next;
102:
103: struct proc *ci_fpproc;
104: int ci_number;
105: int ci_upaid;
106: struct schedstate_percpu ci_schedstate; /* scheduler state */
107:
108: int ci_want_resched;
109:
110: /* DEBUG/DIAGNOSTIC stuff */
111: u_long ci_spin_locks; /* # of spin locks held */
112: u_long ci_simple_locks;/* # of simple locks held */
113:
114: /* Spinning up the CPU */
115: void (*ci_spinup)(void); /* spinup routine */
116: void *ci_initstack;
117: paddr_t ci_paddr; /* Phys addr of this structure. */
118: };
119:
120: extern struct cpu_info *cpus;
121:
122: #define curcpu() ((struct cpu_info *)CPUINFO_VA)
123:
124: #define CPU_IS_PRIMARY(ci) 1
125: #define CPU_INFO_ITERATOR int
126: #define CPU_INFO_FOREACH(cii, ci) \
127: for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL)
128:
129: #define curpcb curcpu()->ci_cpcb
130:
131: /*
132: * definitions of cpu-dependent requirements
133: * referenced in generic code
134: */
135: #define cpu_wait(p) /* nothing */
136: #if 1
137: #define cpu_number() 0
138: #else
139: #define cpu_number() (curcpu()->ci_number)
140: #endif
141:
142: /*
143: * Arguments to hardclock, softclock and gatherstats encapsulate the
144: * previous machine state in an opaque clockframe. The ipl is here
145: * as well for strayintr (see locore.s:interrupt and intr.c:strayintr).
146: * Note that CLKF_INTR is valid only if CLKF_USERMODE is false.
147: */
148: extern int intstack[];
149: extern int eintstack[];
150: struct clockframe {
151: struct trapframe64 t;
152: };
153:
154: #define CLKF_USERMODE(framep) (((framep)->t.tf_tstate & TSTATE_PRIV) == 0)
155: #define CLKF_PC(framep) ((framep)->t.tf_pc)
156: #define CLKF_INTR(framep) ((!CLKF_USERMODE(framep))&&\
157: (((framep)->t.tf_kstack < (vaddr_t)EINTSTACK)&&\
158: ((framep)->t.tf_kstack > (vaddr_t)INTSTACK)))
159:
160: void setsoftnet(void);
161:
162: extern int want_ast;
163:
164: /*
165: * Preempt the current process if in interrupt from user mode,
166: * or after the current trap/syscall if in system mode.
167: */
168: #define need_resched(ci) (ci->ci_want_resched = 1, want_ast = 1)
169:
170: /*
171: * This is used during profiling to integrate system time.
172: */
173: #define PROC_PC(p) ((p)->p_md.md_tf->tf_pc)
174:
175: /*
176: * Give a profiling tick to the current process when the user profiling
177: * buffer pages are invalid. On the sparc, request an ast to send us
178: * through trap(), marking the proc as needing a profiling tick.
179: */
180: #define need_proftick(p) do { want_ast = 1; } while (0)
181:
182: /*
183: * Notify the current process (p) that it has a signal pending,
184: * process as soon as possible.
185: */
186: #define signotify(p) (want_ast = 1)
187:
188: /*
189: * Only one process may own the FPU state.
190: *
191: * XXX this must be per-cpu (eventually)
192: */
193: extern struct proc *fpproc; /* FPU owner */
194: extern int foundfpu; /* true => we have an FPU */
195:
196: /* machdep.c */
197: int ldcontrolb(caddr_t);
198: void dumpconf(void);
199: caddr_t reserve_dumppages(caddr_t);
200: /* clock.c */
201: struct timeval;
202: int tickintr(void *); /* level 10 (tick) interrupt code */
203: int clockintr(void *);/* level 10 (clock) interrupt code */
204: int statintr(void *); /* level 14 (statclock) interrupt code */
205: /* locore.s */
206: struct fpstate64;
207: void savefpstate(struct fpstate64 *);
208: void loadfpstate(struct fpstate64 *);
209: u_int64_t probeget(paddr_t, int, int);
210: #define write_all_windows() __asm __volatile("flushw" : : )
211: #define write_user_windows() __asm __volatile("flushw" : : )
212: void proc_trampoline(void);
213: struct pcb;
214: void snapshot(struct pcb *);
215: struct frame *getfp(void);
216: int xldcontrolb(caddr_t, struct pcb *);
217: void copywords(const void *, void *, size_t);
218: void qcopy(const void *, void *, size_t);
219: void qzero(void *, size_t);
220: void switchtoctx(int);
221: /* locore2.c */
222: void remrq(struct proc *);
223: /* trap.c */
224: void pmap_unuse_final(struct proc *);
225: int rwindow_save(struct proc *);
226: /* amd7930intr.s */
227: void amd7930_trap(void);
228: /* cons.c */
229: int cnrom(void);
230: /* zs.c */
231: void zsconsole(struct tty *, int, int, void (**)(struct tty *, int));
232: #ifdef KGDB
233: void zs_kgdb_init(void);
234: #endif
235: /* fb.c */
236: void fb_unblank(void);
237: /* kgdb_stub.c */
238: #ifdef KGDB
239: void kgdb_attach(int (*)(void *), void (*)(void *, int), void *);
240: void kgdb_connect(int);
241: void kgdb_panic(void);
242: #endif
243: /* emul.c */
244: int fixalign(struct proc *, struct trapframe64 *);
245: int emulinstr(vaddr_t, struct trapframe64 *);
246: int emul_qf(int32_t, struct proc *, union sigval, struct trapframe64 *);
247: int emul_popc(int32_t, struct proc *, union sigval, struct trapframe64 *);
248:
249: /*
250: *
251: * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits
252: * of the trap vector table. The next eight bits are supplied by the
253: * hardware when the trap occurs, and the bottom four bits are always
254: * zero (so that we can shove up to 16 bytes of executable code---exactly
255: * four instructions---into each trap vector).
256: *
257: * The hardware allocates half the trap vectors to hardware and half to
258: * software.
259: *
260: * Traps have priorities assigned (lower number => higher priority).
261: */
262:
263: struct trapvec {
264: int tv_instr[8]; /* the eight instructions */
265: };
266: extern struct trapvec *trapbase; /* the 256 vectors */
267:
268: extern void wzero(void *, u_int);
269: extern void wcopy(const void *, void *, u_int);
270:
271: struct blink_led {
272: void (*bl_func)(void *, int);
273: void *bl_arg;
274: SLIST_ENTRY(blink_led) bl_next;
275: };
276:
277: extern void blink_led_register(struct blink_led *);
278:
279: #endif /* _KERNEL */
280: #endif /* _CPU_H_ */
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