Annotation of sys/arch/sparc64/include/bus.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: bus.h,v 1.23 2007/08/04 16:44:15 kettenis Exp $ */
2: /* $NetBSD: bus.h,v 1.31 2001/09/21 15:30:41 wiz Exp $ */
3:
4: /*-
5: * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10: * NASA Ames Research Center.
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: * 3. All advertising materials mentioning features or use of this software
21: * must display the following acknowledgement:
22: * This product includes software developed by the NetBSD
23: * Foundation, Inc. and its contributors.
24: * 4. Neither the name of The NetBSD Foundation nor the names of its
25: * contributors may be used to endorse or promote products derived
26: * from this software without specific prior written permission.
27: *
28: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38: * POSSIBILITY OF SUCH DAMAGE.
39: */
40:
41: /*
42: * Copyright (c) 1997-1999, 2001 Eduardo E. Horvath. All rights reserved.
43: * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
44: * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
45: *
46: * Redistribution and use in source and binary forms, with or without
47: * modification, are permitted provided that the following conditions
48: * are met:
49: * 1. Redistributions of source code must retain the above copyright
50: * notice, this list of conditions and the following disclaimer.
51: * 2. Redistributions in binary form must reproduce the above copyright
52: * notice, this list of conditions and the following disclaimer in the
53: * documentation and/or other materials provided with the distribution.
54: * 3. All advertising materials mentioning features or use of this software
55: * must display the following acknowledgement:
56: * This product includes software developed by Christopher G. Demetriou
57: * for the NetBSD Project.
58: * 4. The name of the author may not be used to endorse or promote products
59: * derived from this software without specific prior written permission
60: *
61: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
62: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
63: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
64: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
65: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
66: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
67: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
68: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
69: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
70: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
71: */
72:
73: #ifndef _SPARC_BUS_H_
74: #define _SPARC_BUS_H_
75:
76: #include <machine/ctlreg.h>
77:
78: /*
79: * Debug hooks
80: */
81:
82: #define BSDB_ACCESS 0x01
83: #define BSDB_MAP 0x02
84: #define BSDB_ASSERT 0x04
85: #define BSDB_MAPDETAIL 0x08
86: #define BSDB_ALL_ACCESS 0x10
87: extern int bus_space_debug;
88:
89: #define BSHDB_ACCESS 0x01
90: #define BSHDB_NO_ACCESS 0x02
91:
92: #if defined(BUS_SPACE_DEBUG)
93: #ifndef __SYSTM_H__
94: #include <sys/systm.h>
95: #endif
96: #define BUS_SPACE_PRINTF(l, s) do { \
97: if(bus_space_debug & (l)) printf s; \
98: } while(0)
99: #define BUS_SPACE_TRACE(t, h, s) do { \
100: if ( (((bus_space_debug & BSDB_ALL_ACCESS) != 0) && \
101: (((h).bh_flags & BSHDB_NO_ACCESS) == 0)) || \
102: (((bus_space_debug & BSDB_ACCESS) != 0) && \
103: (((h).bh_flags & BSHDB_ACCESS) != 0))) \
104: printf s; \
105: } while(0)
106: #define BUS_SPACE_SET_FLAGS(t, h, f) ((h).bh_flags |= (f))
107: #define BUS_SPACE_CLEAR_FLAGS(t, h, f) ((h).bh_flags &= ~(f))
108: #define BUS_SPACE_FLAG_DECL(s) int s
109: #define BUS_SPACE_SAVE_FLAGS(t, h, s) (s = (h).bh_flags)
110: #define BUS_SPACE_RESTORE_FLAGS(t, h, s) (s = (h).bh_flags)
111: #define BUS_SPACE_ASSERT(t, h, o, n) do { \
112: if (bus_space_debug & BSDB_ASSERT) \
113: bus_space_assert(t, &(h), o, n); \
114: } while(0)
115: #else /* BUS_SPACE_DEBUG */
116: #define BUS_SPACE_PRINTF(l, s)
117: #define BUS_SPACE_TRACE(t, h, s)
118: #define BUS_SPACE_SET_FLAGS(t, h, f)
119: #define BUS_SPACE_CLEAR_FLAGS(t, h, f)
120: #define BUS_SPACE_FLAG_DECL(s)
121: #define BUS_SPACE_SAVE_FLAGS(t, h, s)
122: #define BUS_SPACE_RESTORE_FLAGS(t, h, s)
123: #define BUS_SPACE_ASSERT(t, h, o, n)
124: #endif /* BUS_SPACE_DEBUG */
125:
126:
127: /*
128: * UPA and SBus spaces are non-cached and big endian
129: * (except for RAM and PROM)
130: *
131: * PCI spaces are non-cached and little endian
132: */
133:
134: enum bus_type {
135: UPA_BUS_SPACE,
136: SBUS_BUS_SPACE,
137: PCI_CONFIG_BUS_SPACE,
138: PCI_IO_BUS_SPACE,
139: PCI_MEMORY_BUS_SPACE,
140: LAST_BUS_SPACE
141: };
142: /* For backwards compatibility */
143: #define SPARC_BUS_SPACE UPA_BUS_SPACE
144:
145: /*
146: * Bus address and size types
147: */
148: typedef const struct sparc_bus_space_tag *bus_space_tag_t;
149: typedef u_int64_t bus_addr_t;
150: typedef u_int64_t bus_size_t;
151:
152:
153: typedef struct _bus_space_handle {
154: paddr_t bh_ptr;
155: #ifdef BUS_SPACE_DEBUG
156: bus_space_tag_t bh_tag;
157: bus_size_t bh_size;
158: int bh_flags;
159: #endif
160: } bus_space_handle_t;
161:
162: /* For buses which have an iospace. */
163: #define BUS_ADDR_IOSPACE(x) ((x)>>32)
164: #define BUS_ADDR_PADDR(x) ((x)&0xffffffff)
165: #define BUS_ADDR(io, pa) ((((bus_addr_t)io)<<32)|(pa))
166:
167: /*
168: * Access methods for bus resources and address space.
169: */
170:
171: struct sparc_bus_space_tag {
172: void *cookie;
173: bus_space_tag_t parent;
174: enum bus_type default_type;
175: u_int8_t asi;
176: u_int8_t sasi;
177: char name[32];
178:
179: int (*sparc_bus_alloc)(bus_space_tag_t,
180: bus_space_tag_t,
181: bus_addr_t, bus_addr_t,
182: bus_size_t, bus_size_t, bus_size_t,
183: int, bus_addr_t *, bus_space_handle_t *);
184:
185: void (*sparc_bus_free)(bus_space_tag_t,
186: bus_space_tag_t,
187: bus_space_handle_t, bus_size_t);
188:
189: int (*sparc_bus_map)(bus_space_tag_t,
190: bus_space_tag_t,
191: bus_addr_t, bus_size_t,
192: int, bus_space_handle_t *);
193:
194: int (*sparc_bus_protect)(bus_space_tag_t,
195: bus_space_tag_t,
196: bus_space_handle_t, bus_size_t, int);
197:
198: int (*sparc_bus_unmap)(bus_space_tag_t,
199: bus_space_tag_t,
200: bus_space_handle_t, bus_size_t);
201:
202: int (*sparc_bus_subregion)(bus_space_tag_t,
203: bus_space_tag_t,
204: bus_space_handle_t, bus_size_t,
205: bus_size_t, bus_space_handle_t *);
206:
207: void (*sparc_bus_barrier)(bus_space_tag_t,
208: bus_space_tag_t,
209: bus_space_handle_t, bus_size_t,
210: bus_size_t, int);
211:
212: paddr_t (*sparc_bus_mmap)(bus_space_tag_t,
213: bus_space_tag_t,
214: bus_addr_t, off_t, int, int);
215:
216: void *(*sparc_intr_establish)(bus_space_tag_t,
217: bus_space_tag_t,
218: int, int, int,
219: int (*)(void *), void *,
220: const char *);
221:
222: bus_addr_t (*sparc_bus_addr)(bus_space_tag_t,
223: bus_space_tag_t, bus_space_handle_t);
224: };
225:
226: /*
227: * Bus space function prototypes.
228: */
229: int bus_space_alloc(
230: bus_space_tag_t,
231: bus_addr_t, /* reg start */
232: bus_addr_t, /* reg end */
233: bus_size_t, /* size */
234: bus_size_t, /* alignment */
235: bus_size_t, /* boundary */
236: int, /* flags */
237: bus_addr_t *,
238: bus_space_handle_t *);
239: void bus_space_free(
240: bus_space_tag_t,
241: bus_space_handle_t,
242: bus_size_t);
243: int bus_space_map(
244: bus_space_tag_t,
245: bus_addr_t,
246: bus_size_t,
247: int, /*flags*/
248: bus_space_handle_t *);
249: int bus_space_protect(
250: bus_space_tag_t,
251: bus_space_handle_t,
252: bus_size_t,
253: int); /*flags*/
254: int bus_space_unmap(
255: bus_space_tag_t,
256: bus_space_handle_t,
257: bus_size_t);
258: int bus_space_subregion(
259: bus_space_tag_t,
260: bus_space_handle_t,
261: bus_size_t,
262: bus_size_t,
263: bus_space_handle_t *);
264: static void bus_space_barrier(
265: bus_space_tag_t,
266: bus_space_handle_t,
267: bus_size_t,
268: bus_size_t,
269: int);
270: paddr_t bus_space_mmap(
271: bus_space_tag_t,
272: bus_addr_t, /*addr*/
273: off_t, /*offset*/
274: int, /*prot*/
275: int); /*flags*/
276: void *bus_intr_establish(
277: bus_space_tag_t,
278: int, /*bus-specific intr*/
279: int, /*device class level,
280: see machine/intr.h*/
281: int, /*flags*/
282: int (*)(void *), /*handler*/
283: void *, /*handler arg*/
284: const char *); /*what*/
285: void *bus_intr_allocate(
286: bus_space_tag_t,
287: int (*)(void *), /*handler*/
288: void *, /*handler arg*/
289: int, /*number*/
290: int, /*pil*/
291: volatile u_int64_t *, /*map*/
292: volatile u_int64_t *, /*clr*/
293: const char *); /*what*/
294: void bus_intr_free(void *);
295: void bus_space_render_tag(
296: bus_space_tag_t,
297: char *,
298: size_t);
299: void *bus_space_vaddr(
300: bus_space_tag_t,
301: bus_space_handle_t);
302:
303: #ifdef BUS_SPACE_DEBUG
304: void bus_space_assert(bus_space_tag_t,
305: const bus_space_handle_t *,
306: bus_size_t, int);
307: void bus_space_render_tag(bus_space_tag_t, char*, size_t);
308: #endif /* BUS_SPACE_DEBUG */
309:
310:
311: #define _BS_PRECALL(t,f) \
312: while (t->f == NULL) \
313: t = t->parent;
314: #define _BS_POSTCALL
315:
316: #define _BS_CALL(t,f) \
317: (*(t)->f)
318:
319: static inline void
320: bus_space_barrier(t, h, o, s, f)
321: bus_space_tag_t t;
322: bus_space_handle_t h;
323: bus_size_t o;
324: bus_size_t s;
325: int f;
326: {
327: const bus_space_tag_t t0 = t;
328: _BS_PRECALL(t, sparc_bus_barrier);
329: _BS_CALL(t, sparc_bus_barrier)(t, t0, h, o, s, f);
330: _BS_POSTCALL;
331: }
332:
333: #include <sparc64/sparc64/busop.h>
334:
335: /* flags for bus space map functions */
336: #define BUS_SPACE_MAP_CACHEABLE 0x0001
337: #define BUS_SPACE_MAP_LINEAR 0x0002
338: #define BUS_SPACE_MAP_READONLY 0x0004
339: #define BUS_SPACE_MAP_PREFETCHABLE 0x0008
340: #define BUS_SPACE_MAP_PROMADDRESS 0x0010
341: #define BUS_SPACE_MAP_BUS1 0x0100 /* placeholders for bus functions... */
342: #define BUS_SPACE_MAP_BUS2 0x0200
343: #define BUS_SPACE_MAP_BUS3 0x0400
344: #define BUS_SPACE_MAP_BUS4 0x0800
345:
346:
347: /* flags for intr_establish() */
348: #define BUS_INTR_ESTABLISH_FASTTRAP 1
349: #define BUS_INTR_ESTABLISH_SOFTINTR 2
350:
351: /* flags for bus_space_barrier() */
352: #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
353: #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
354:
355: /*
356: * Flags used in various bus DMA methods.
357: */
358: #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
359: #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
360: #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
361: #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */
362: #define BUS_DMA_NOWRITE 0x008 /* I suppose the following two should default on */
363: #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
364: #define BUS_DMA_BUS2 0x020
365: #define BUS_DMA_BUS3 0x040
366: #define BUS_DMA_BUS4 0x080
367: #define BUS_DMA_STREAMING 0x100 /* hint: sequential, unidirectional */
368: #define BUS_DMA_READ 0x200 /* mapping is device -> memory only */
369: #define BUS_DMA_WRITE 0x400 /* mapping is memory -> device only */
370:
371: #define BUS_DMA_NOCACHE BUS_DMA_BUS1
372: #define BUS_DMA_DVMA BUS_DMA_BUS2 /* Don't bother with alignment */
373: #define BUS_DMA_24BIT BUS_DMA_BUS3 /* 24bit device */
374:
375: #define BUS_DMA_RAW BUS_DMA_STREAMING
376:
377: /* Forwards needed by prototypes below. */
378: struct mbuf;
379: struct uio;
380:
381: /*
382: * Operations performed by bus_dmamap_sync().
383: */
384: #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
385: #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
386: #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
387: #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
388:
389: typedef struct sparc_bus_dma_tag *bus_dma_tag_t;
390: typedef struct sparc_bus_dmamap *bus_dmamap_t;
391:
392: /*
393: * bus_dma_segment_t
394: *
395: * Describes a single contiguous DMA transaction. Values
396: * are suitable for programming into DMA registers.
397: */
398: struct sparc_bus_dma_segment {
399: bus_addr_t ds_addr; /* DVMA address */
400: bus_size_t ds_len; /* length of transfer */
401: /*
402: * The following is to support bus_dmamem_alloc()'s
403: * odd interface. Only the values in the first
404: * segment are used. This means that 3/5ths of
405: * most segments are useless space (and mbufs use 1024
406: * segments).
407: */
408: bus_size_t _ds_boundary; /* don't cross this */
409: bus_size_t _ds_align; /* align to this */
410: void *_ds_mlist; /* XXX - dmamap_alloc'ed pages */
411: };
412: typedef struct sparc_bus_dma_segment bus_dma_segment_t;
413:
414:
415: /*
416: * bus_dma_tag_t
417: *
418: * A machine-dependent opaque type describing the implementation of
419: * DMA for a given bus.
420: */
421: struct sparc_bus_dma_tag {
422: void *_cookie; /* cookie used in the guts */
423: struct sparc_bus_dma_tag* _parent;
424:
425: /*
426: * DMA mapping methods.
427: */
428: int (*_dmamap_create)(bus_dma_tag_t, bus_dma_tag_t, bus_size_t,
429: int, bus_size_t, bus_size_t, int, bus_dmamap_t *);
430: void (*_dmamap_destroy)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t);
431: int (*_dmamap_load)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t,
432: void *, bus_size_t, struct proc *, int);
433: int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dma_tag_t,
434: bus_dmamap_t, struct mbuf *, int);
435: int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t,
436: struct uio *, int);
437: int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t,
438: bus_dma_segment_t *, int, bus_size_t, int);
439: void (*_dmamap_unload)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t);
440: void (*_dmamap_sync)(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t,
441: bus_addr_t, bus_size_t, int);
442:
443: /*
444: * DMA memory utility functions.
445: */
446: int (*_dmamem_alloc)(bus_dma_tag_t, bus_dma_tag_t, bus_size_t,
447: bus_size_t, bus_size_t, bus_dma_segment_t *, int, int *,
448: int);
449: void (*_dmamem_free)(bus_dma_tag_t, bus_dma_tag_t,
450: bus_dma_segment_t *, int);
451: int (*_dmamem_map)(bus_dma_tag_t, bus_dma_tag_t,
452: bus_dma_segment_t *, int, size_t, caddr_t *, int);
453: void (*_dmamem_unmap)(bus_dma_tag_t, bus_dma_tag_t, caddr_t,
454: size_t);
455: paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_tag_t,
456: bus_dma_segment_t *, int, off_t, int, int);
457: };
458:
459: #define _BD_PRECALL(t,f) \
460: while (t->f == NULL) { \
461: t = t->_parent; \
462: }
463: #define _BD_CALL(t,f) \
464: (*(t)->f)
465: #define _BD_POSTCALL
466:
467: static inline int
468: bus_dmamap_create(bus_dma_tag_t t, bus_size_t s, int n, bus_size_t m,
469: bus_size_t b, int f, bus_dmamap_t *p)
470: {
471: int r;
472: const bus_dma_tag_t t0 = t;
473: _BD_PRECALL(t, _dmamap_create);
474: r = _BD_CALL(t, _dmamap_create)(t, t0, s, n, m, b, f, p);
475: _BD_POSTCALL;
476: return (r);
477: }
478: static inline void
479: bus_dmamap_destroy(bus_dma_tag_t t, bus_dmamap_t p)
480: {
481: const bus_dma_tag_t t0 = t;
482: _BD_PRECALL(t, _dmamap_destroy);
483: _BD_CALL(t, _dmamap_destroy)(t, t0, p);
484: _BD_POSTCALL;
485: }
486: static inline int
487: bus_dmamap_load(bus_dma_tag_t t, bus_dmamap_t m, void *b, bus_size_t s,
488: struct proc *p, int f)
489: {
490: const bus_dma_tag_t t0 = t;
491: int r;
492: _BD_PRECALL(t, _dmamap_load);
493: r = _BD_CALL(t, _dmamap_load)(t, t0, m, b, s, p, f);
494: _BD_POSTCALL;
495: return (r);
496: }
497: static inline int
498: bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t m, struct mbuf *b,
499: int f)
500: {
501: const bus_dma_tag_t t0 = t;
502: int r;
503: _BD_PRECALL(t, _dmamap_load_mbuf);
504: r = _BD_CALL(t, _dmamap_load_mbuf)(t, t0, m, b, f);
505: _BD_POSTCALL;
506: return (r);
507: }
508: static inline int
509: bus_dmamap_load_uio(bus_dma_tag_t t, bus_dmamap_t m, struct uio * u, int f)
510: {
511: const bus_dma_tag_t t0 = t;
512: int r;
513: _BD_PRECALL(t, _dmamap_load_uio);
514: r = _BD_CALL(t, _dmamap_load_uio)(t, t0, m, u, f);
515: _BD_POSTCALL;
516: return (r);
517: }
518: static inline int
519: bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t m, bus_dma_segment_t *sg,
520: int n, bus_size_t s, int f)
521: {
522: const bus_dma_tag_t t0 = t;
523: int r;
524: _BD_PRECALL(t, _dmamap_load_raw);
525: r = _BD_CALL(t, _dmamap_load_raw)(t, t0, m, sg, n, s, f);
526: _BD_POSTCALL;
527: return (r);
528: }
529: static inline void
530: bus_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t p)
531: {
532: const bus_dma_tag_t t0 = t;
533: _BD_PRECALL(t, _dmamap_unload);
534: _BD_CALL(t, _dmamap_unload)(t, t0, p);
535: _BD_POSTCALL;
536: }
537: static inline void
538: bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t p, bus_addr_t o, bus_size_t l,
539: int ops)
540: {
541: const bus_dma_tag_t t0 = t;
542: _BD_PRECALL(t, _dmamap_sync);
543: _BD_CALL(t, _dmamap_sync)(t, t0, p, o, l, ops);
544: _BD_POSTCALL;
545: }
546: static inline int
547: bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t s, bus_size_t a, bus_size_t b,
548: bus_dma_segment_t *sg, int n, int *r, int f)
549: {
550: const bus_dma_tag_t t0 = t;
551: int ret;
552: _BD_PRECALL(t, _dmamem_alloc);
553: ret = _BD_CALL(t, _dmamem_alloc)(t, t0, s, a, b, sg, n, r, f);
554: _BD_POSTCALL;
555: return (ret);
556: }
557: static inline void
558: bus_dmamem_free(bus_dma_tag_t t, bus_dma_segment_t *sg, int n)
559: {
560: const bus_dma_tag_t t0 = t;
561: _BD_PRECALL(t, _dmamem_free);
562: _BD_CALL(t, _dmamem_free)(t, t0, sg, n);
563: _BD_POSTCALL;
564: }
565: static inline int
566: bus_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *sg, int n, size_t s,
567: caddr_t *k, int f)
568: {
569: const bus_dma_tag_t t0 = t;
570: int r;
571: _BD_PRECALL(t, _dmamem_map);
572: r = _BD_CALL(t, _dmamem_map)(t, t0, sg, n, s, k, f);
573: _BD_POSTCALL;
574: return (r);
575: }
576: static inline void
577: bus_dmamem_unmap(bus_dma_tag_t t, caddr_t k, size_t s)
578: {
579: const bus_dma_tag_t t0 = t;
580: _BD_PRECALL(t, _dmamem_unmap);
581: _BD_CALL(t, _dmamem_unmap)(t, t0, k, s);
582: _BD_POSTCALL;
583: }
584: static inline paddr_t
585: bus_dmamem_mmap(bus_dma_tag_t t, bus_dma_segment_t *sg, int n, off_t o, int p,
586: int f)
587: {
588: const bus_dma_tag_t t0 = t;
589: int r;
590: _BD_PRECALL(t, _dmamem_mmap);
591: r = _BD_CALL(t, _dmamem_mmap)(t, t0, sg, n, o, p, f);
592: _BD_POSTCALL;
593: return (r);
594: }
595:
596: /*
597: * bus_dmamap_t
598: *
599: * Describes a DMA mapping.
600: */
601: struct sparc_bus_dmamap {
602: /*
603: * PRIVATE MEMBERS: not for use by machine-independent code.
604: */
605: bus_addr_t _dm_dvmastart; /* start and size of allocated */
606: bus_size_t _dm_dvmasize; /* DVMA segment for this map */
607:
608: bus_size_t _dm_size; /* largest DMA transfer mappable */
609: bus_size_t _dm_maxsegsz; /* largest possible segment */
610: bus_size_t _dm_boundary; /* don't cross this */
611: int _dm_segcnt; /* number of segs this map can map */
612: int _dm_flags; /* misc. flags */
613: #define _DM_TYPE_LOAD 0
614: #define _DM_TYPE_SEGS 1
615: #define _DM_TYPE_UIO 2
616: #define _DM_TYPE_MBUF 3
617: int _dm_type; /* mapping type: raw, uio, mbuf, etc */
618: void *_dm_source; /* source mbuf/uio/etc. for unload */
619:
620: void *_dm_cookie; /* cookie for bus-specific functions */
621:
622: /*
623: * PUBLIC MEMBERS: these are used by machine-independent code.
624: */
625: bus_size_t dm_mapsize; /* size of the mapping */
626: int dm_nsegs; /* # valid segments in mapping */
627:
628: bus_dma_segment_t dm_segs[1]; /* segments; variable length */
629: };
630:
631: #endif /* _SPARC_BUS_H_ */
632:
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