Annotation of sys/arch/sparc64/fpu/fpu_emu.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: fpu_emu.h,v 1.5 2006/06/21 19:24:38 jason Exp $ */
! 2: /* $NetBSD: fpu_emu.h,v 1.4 2000/08/03 18:32:07 eeh Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1992, 1993
! 6: * The Regents of the University of California. All rights reserved.
! 7: *
! 8: * This software was developed by the Computer Systems Engineering group
! 9: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
! 10: * contributed to Berkeley.
! 11: *
! 12: * All advertising materials mentioning features or use of this software
! 13: * must display the following acknowledgement:
! 14: * This product includes software developed by the University of
! 15: * California, Lawrence Berkeley Laboratory.
! 16: *
! 17: * Redistribution and use in source and binary forms, with or without
! 18: * modification, are permitted provided that the following conditions
! 19: * are met:
! 20: * 1. Redistributions of source code must retain the above copyright
! 21: * notice, this list of conditions and the following disclaimer.
! 22: * 2. Redistributions in binary form must reproduce the above copyright
! 23: * notice, this list of conditions and the following disclaimer in the
! 24: * documentation and/or other materials provided with the distribution.
! 25: * 3. Neither the name of the University nor the names of its contributors
! 26: * may be used to endorse or promote products derived from this software
! 27: * without specific prior written permission.
! 28: *
! 29: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 30: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 31: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 32: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 33: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 37: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 38: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 39: * SUCH DAMAGE.
! 40: *
! 41: * @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93
! 42: */
! 43:
! 44: /*
! 45: * Floating point emulator (tailored for SPARC, but structurally
! 46: * machine-independent).
! 47: *
! 48: * Floating point numbers are carried around internally in an `expanded'
! 49: * or `unpacked' form consisting of:
! 50: * - sign
! 51: * - unbiased exponent
! 52: * - mantissa (`1.' + 112-bit fraction + guard + round)
! 53: * - sticky bit
! 54: * Any implied `1' bit is inserted, giving a 113-bit mantissa that is
! 55: * always nonzero. Additional low-order `guard' and `round' bits are
! 56: * scrunched in, making the entire mantissa 115 bits long. This is divided
! 57: * into four 32-bit words, with `spare' bits left over in the upper part
! 58: * of the top word (the high bits of fp_mant[0]). An internal `exploded'
! 59: * number is thus kept within the half-open interval [1.0,2.0) (but see
! 60: * the `number classes' below). This holds even for denormalized numbers:
! 61: * when we explode an external denorm, we normalize it, introducing low-order
! 62: * zero bits, so that the rest of the code always sees normalized values.
! 63: *
! 64: * Note that a number of our algorithms use the `spare' bits at the top.
! 65: * The most demanding algorithm---the one for sqrt---depends on two such
! 66: * bits, so that it can represent values up to (but not including) 8.0,
! 67: * and then it needs a carry on top of that, so that we need three `spares'.
! 68: *
! 69: * The sticky-word is 32 bits so that we can use `OR' operators to goosh
! 70: * whole words from the mantissa into it.
! 71: *
! 72: * All operations are done in this internal extended precision. According
! 73: * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is,
! 74: * it is OK to do a+b in extended precision and then round the result to
! 75: * single precision---provided single, double, and extended precisions are
! 76: * `far enough apart' (they always are), but we will try to avoid any such
! 77: * extra work where possible.
! 78: */
! 79: struct fpn {
! 80: int fp_class; /* see below */
! 81: int fp_sign; /* 0 => positive, 1 => negative */
! 82: int fp_exp; /* exponent (unbiased) */
! 83: int fp_sticky; /* nonzero bits lost at right end */
! 84: u_int fp_mant[4]; /* 115-bit mantissa */
! 85: };
! 86:
! 87: #define FP_NMANT 115 /* total bits in mantissa (incl g,r) */
! 88: #define FP_NG 2 /* number of low-order guard bits */
! 89: #define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */
! 90: #define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */
! 91: #define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */
! 92: #define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */
! 93: #define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */
! 94:
! 95: /*
! 96: * Number classes. Since zero, Inf, and NaN cannot be represented using
! 97: * the above layout, we distinguish these from other numbers via a class.
! 98: * In addition, to make computation easier and to follow Appendix N of
! 99: * the SPARC Version 8 standard, we give each kind of NaN a separate class.
! 100: */
! 101: #define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */
! 102: #define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */
! 103: #define FPC_ZERO 0 /* zero (sign matters) */
! 104: #define FPC_NUM 1 /* number (sign matters) */
! 105: #define FPC_INF 2 /* infinity (sign matters) */
! 106:
! 107: #define ISNAN(fp) ((fp)->fp_class < 0)
! 108: #define ISZERO(fp) ((fp)->fp_class == 0)
! 109: #define ISINF(fp) ((fp)->fp_class == FPC_INF)
! 110:
! 111: /*
! 112: * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points
! 113: * to the `more significant' operand for our purposes. Appendix N says that
! 114: * the result of a computation involving two numbers are:
! 115: *
! 116: * If both are SNaN: operand 2, converted to Quiet
! 117: * If only one is SNaN: the SNaN operand, converted to Quiet
! 118: * If both are QNaN: operand 2
! 119: * If only one is QNaN: the QNaN operand
! 120: *
! 121: * In addition, in operations with an Inf operand, the result is usually
! 122: * Inf. The class numbers are carefully arranged so that if
! 123: * (unsigned)class(op1) > (unsigned)class(op2)
! 124: * then op1 is the one we want; otherwise op2 is the one we want.
! 125: */
! 126: #define ORDER(x, y) { \
! 127: if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \
! 128: SWAP(x, y); \
! 129: }
! 130: #define SWAP(x, y) { \
! 131: register struct fpn *swap; \
! 132: swap = (x), (x) = (y), (y) = swap; \
! 133: }
! 134:
! 135: /*
! 136: * Emulator state.
! 137: */
! 138: struct fpemu {
! 139: struct fpstate64 *fe_fpstate; /* registers, etc */
! 140: int fe_fsr; /* fsr copy (modified during op) */
! 141: int fe_cx; /* exceptions */
! 142: struct fpn fe_f1; /* operand 1 */
! 143: struct fpn fe_f2; /* operand 2, if required */
! 144: struct fpn fe_f3; /* available storage for result */
! 145: };
! 146:
! 147: /*
! 148: * Arithmetic functions.
! 149: * Each of these may modify its inputs (f1,f2) and/or the temporary.
! 150: * Each returns a pointer to the result and/or sets exceptions.
! 151: */
! 152: struct fpn *fpu_add(struct fpemu *);
! 153: #define fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, fpu_add(fe))
! 154: struct fpn *fpu_mul(struct fpemu *);
! 155: struct fpn *fpu_div(struct fpemu *);
! 156: struct fpn *fpu_sqrt(struct fpemu *);
! 157:
! 158: /*
! 159: * Other functions.
! 160: */
! 161:
! 162: /* Perform a compare instruction (with or without unordered exception). */
! 163: void fpu_compare(struct fpemu *, int);
! 164:
! 165: /* Build a new Quiet NaN (sign=0, frac=all 1's). */
! 166: struct fpn *fpu_newnan(struct fpemu *);
! 167:
! 168: /*
! 169: * Shift a number right some number of bits, taking care of round/sticky.
! 170: * Note that the result is probably not a well-formed number (it will lack
! 171: * the normal 1-bit mant[0]&FP_1).
! 172: */
! 173: int fpu_shr(struct fpn *, int);
! 174:
! 175: void fpu_explode(struct fpemu *, struct fpn *, int, int);
! 176: void fpu_implode(struct fpemu *, struct fpn *, int, u_int *);
! 177:
! 178: #ifdef DEBUG
! 179: #define FPE_INSN 0x1
! 180: #define FPE_REG 0x2
! 181: #define FPE_STATE 0x4
! 182: extern int fpe_debug;
! 183: void fpu_dumpfpn(struct fpn *);
! 184: void fpu_dumpstate(struct fpstate64 *);
! 185: #define DPRINTF(x, y) if (fpe_debug & (x)) printf y
! 186: #define DUMPFPN(x, f) if (fpe_debug & (x)) fpu_dumpfpn((f))
! 187: #define DUMPSTATE(x, s) if (fpe_debug & (x)) fpu_dumpstate((s))
! 188: #else
! 189: #define DPRINTF(x, y)
! 190: #define DUMPFPN(x, f)
! 191: #define DUMPSTATE(x, s)
! 192: #endif
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