Annotation of sys/arch/sparc64/dev/schizoreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: schizoreg.h,v 1.18 2007/01/20 16:26:53 kettenis Exp $ */
2:
3: /*
4: * Copyright (c) 2002 Jason L. Wright (jason@thought.net)
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
25: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26: * POSSIBILITY OF SUCH DAMAGE.
27: */
28: struct schizo_pbm_regs {
29: volatile u_int64_t _unused1[64]; /* 0x0000 - 0x01ff */
30: struct iommureg iommu; /* 0x0200 - 0x0217 */
31: volatile u_int64_t iommu_ctxflush; /* 0x0218 - 0x021f */
32: volatile u_int64_t _unused2[444];
33: volatile u_int64_t imap[64];
34: volatile u_int64_t _unused3[64];
35: volatile u_int64_t iclr[64];
36: volatile u_int64_t _unused4[320];
37: volatile u_int64_t ctrl;
38: volatile u_int64_t __unused0;
39: volatile u_int64_t afsr;
40: volatile u_int64_t afar;
41: volatile u_int64_t _unused5[252];
42: struct iommu_strbuf strbuf;
43: volatile u_int64_t strbuf_ctxflush;
44: volatile u_int64_t _unused6[4012];
45: volatile u_int64_t iommu_tag;
46: volatile u_int64_t _unused7[15];
47: volatile u_int64_t iommu_data;
48: volatile u_int64_t _unused8[2879];
49: volatile u_int64_t strbuf_ctxmatch;
50: volatile u_int64_t _unused9[122879];
51: };
52:
53: struct schizo_regs {
54: volatile u_int64_t _unused0[8];
55: volatile u_int64_t pcia_mem_match;
56: volatile u_int64_t pcia_mem_mask;
57: volatile u_int64_t pcia_io_match;
58: volatile u_int64_t pcia_io_mask;
59: volatile u_int64_t pcib_mem_match;
60: volatile u_int64_t pcib_mem_mask;
61: volatile u_int64_t pcib_io_match;
62: volatile u_int64_t pcib_io_mask;
63: volatile u_int64_t _unused1[8176];
64:
65: volatile u_int64_t control_status;
66: volatile u_int64_t error_control;
67: volatile u_int64_t interrupt_control;
68: volatile u_int64_t safari_errlog;
69: volatile u_int64_t eccctrl;
70: volatile u_int64_t _unused3[1];
71: volatile u_int64_t ue_afsr;
72: volatile u_int64_t ue_afar;
73: volatile u_int64_t ce_afsr;
74: volatile u_int64_t ce_afar;
75:
76: volatile u_int64_t _unused4[253942];
77: struct schizo_pbm_regs pbm_a;
78: struct schizo_pbm_regs pbm_b;
79: };
80:
81: #define SCZ_PCIA_MEM_MATCH 0x00040
82: #define SCZ_PCIA_MEM_MASK 0x00048
83: #define SCZ_PCIA_IO_MATCH 0x00050
84: #define SCZ_PCIA_IO_MASK 0x00058
85: #define SCZ_PCIB_MEM_MATCH 0x00060
86: #define SCZ_PCIB_MEM_MASK 0x00068
87: #define SCZ_PCIB_IO_MATCH 0x00070
88: #define SCZ_PCIB_IO_MASK 0x00078
89: #define SCZ_CONTROL_STATUS 0x10000
90: #define SCZ_SAFARI_INTCTRL 0x10010
91: #define SCZ_SAFARI_ERRLOG 0x10018
92: #define SCZ_ECCCTRL 0x10020
93: #define SCZ_UE_AFSR 0x10030
94: #define SCZ_UE_AFAR 0x10038
95: #define SCZ_CE_AFSR 0x10040
96: #define SCZ_CE_AFAR 0x10048
97:
98: /* These are relative to the PBM */
99: #define SCZ_PCI_IOMMU_CTRL 0x00200
100: #define SCZ_PCI_IOMMU_TSBBASE 0x00208
101: #define SCZ_PCI_IOMMU_FLUSH 0x00210
102: #define SCZ_PCI_IOMMU_CTXFLUSH 0x00218
103: #define TOM_PCI_IOMMU_TFAR 0x00220
104: #define SCZ_PCI_IMAP_BASE 0x01000
105: #define SCZ_PCI_ICLR_BASE 0x01400
106: #define SCZ_PCI_INTR_RETRY 0x01a00 /* interrupt retry */
107: #define SCZ_PCI_DMA_FLUSH 0x01a08 /* pci consistent dma flush */
108: #define SCZ_PCI_CTRL 0x02000
109: #define SCZ_PCI_AFSR 0x02010
110: #define SCZ_PCI_AFAR 0x02018
111: #define SCZ_PCI_DIAG 0x02020
112: #define SCZ_PCI_ESTAR 0x02028
113: #define SCZ_PCI_STRBUF_CTRL 0x02800
114: #define SCZ_PCI_STRBUF_FLUSH 0x02808
115: #define SCZ_PCI_STRBUF_FSYNC 0x02810
116: #define SCZ_PCI_STRBUF_CTXFLUSH 0x02818
117: #define SCZ_PCI_IOMMU_TAG 0x0a580
118: #define SCZ_PCI_IOMMU_DATA 0x0a600
119: #define SCZ_PCI_STRBUF_CTXMATCH 0x10000
120:
121: #define SCZ_ECCCTRL_EE_INTEN 0x8000000000000000UL
122: #define SCZ_ECCCTRL_UE_INTEN 0x4000000000000000UL
123: #define SCZ_ECCCTRL_CE_INTEN 0x2000000000000000UL
124:
125: #define SCZ_UEAFSR_PPIO 0x8000000000000000UL
126: #define SCZ_UEAFSR_PDRD 0x4000000000000000UL
127: #define SCZ_UEAFSR_PDWR 0x2000000000000000UL
128: #define SCZ_UEAFSR_SPIO 0x1000000000000000UL
129: #define SCZ_UEAFSR_SDMA 0x0800000000000000UL
130: #define SCZ_UEAFSR_ERRPNDG 0x0300000000000000UL
131: #define SCZ_UEAFSR_BMSK 0x000003ff00000000UL
132: #define SCZ_UEAFSR_QOFF 0x00000000c0000000UL
133: #define SCZ_UEAFSR_AID 0x000000001f000000UL
134: #define SCZ_UEAFSR_PARTIAL 0x0000000000800000UL
135: #define SCZ_UEAFSR_OWNEDIN 0x0000000000400000UL
136: #define SCZ_UEAFSR_MTAGSYND 0x00000000000f0000UL
137: #define SCZ_UEAFSR_MTAG 0x000000000000e000UL
138: #define SCZ_UEAFSR_ECCSYND 0x00000000000001ffUL
139:
140: #define SCZ_UEAFAR_PIO 0x0000080000000000UL /* 0=pio, 1=memory */
141: #define SCZ_UEAFAR_PIO_TYPE 0x0000078000000000UL /* pio type: */
142: #define SCZ_UEAFAR_PIO_UPA 0x0000078000000000UL /* upa */
143: #define SZC_UEAFAR_PIO_SAFARI 0x0000060000000000UL /* safari/upa64s */
144: #define SCZ_UEAFAR_PIO_NLAS 0x0000058000000000UL /* newlink alt space */
145: #define SCZ_UEAFAR_PIO_NLS 0x0000050000000000UL /* newlink space */
146: #define SCZ_UEAFAR_PIO_NLI 0x0000040000000000UL /* newlink interface */
147: #define SCZ_UEAFAR_PIO_PCIAM 0x0000030000000000UL /* pcia: memory */
148: #define SCZ_UEAFAR_PIO_PCIAI 0x0000020000000000UL /* pcia: interface */
149: #define SZC_UEAFAR_PIO_PCIBC 0x0000018000000000UL /* pcia: config / i/o */
150: #define SZC_UEAFAR_PIO_PCIBM 0x0000010000000000UL /* pcib: memory */
151: #define SZC_UEAFAR_PIO_PCIBI 0x0000000000000000UL /* pcib: interface */
152: #define SCZ_UEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */
153: #define SCZ_UEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */
154:
155: #define SCZ_CEAFSR_PPIO 0x8000000000000000UL
156: #define SCZ_CEAFSR_PDRD 0x4000000000000000UL
157: #define SCZ_CEAFSR_PDWR 0x2000000000000000UL
158: #define SCZ_CEAFSR_SPIO 0x1000000000000000UL
159: #define SCZ_CEAFSR_SDMA 0x0800000000000000UL
160: #define SCZ_CEAFSR_ERRPNDG 0x0300000000000000UL
161: #define SCZ_CEAFSR_BMSK 0x000003ff00000000UL
162: #define SCZ_CEAFSR_QOFF 0x00000000c0000000UL
163: #define SCZ_CEAFSR_AID 0x000000001f000000UL
164: #define SCZ_CEAFSR_PARTIAL 0x0000000000800000UL
165: #define SCZ_CEAFSR_OWNEDIN 0x0000000000400000UL
166: #define SCZ_CEAFSR_MTAGSYND 0x00000000000f0000UL
167: #define SCZ_CEAFSR_MTAG 0x000000000000e000UL
168: #define SCZ_CEAFSR_ECCSYND 0x00000000000001ffUL
169:
170: #define SCZ_CEAFAR_PIO 0x0000080000000000UL /* 0=pio, 1=memory */
171: #define SCZ_CEAFAR_PIO_TYPE 0x0000078000000000UL /* pio type: */
172: #define SCZ_CEAFAR_PIO_UPA 0x0000078000000000UL /* upa */
173: #define SZC_CEAFAR_PIO_SAFARI 0x0000060000000000UL /* safari/upa64s */
174: #define SCZ_CEAFAR_PIO_NLAS 0x0000058000000000UL /* newlink alt space */
175: #define SCZ_CEAFAR_PIO_NLS 0x0000050000000000UL /* newlink space */
176: #define SCZ_CEAFAR_PIO_NLI 0x0000040000000000UL /* newlink interface */
177: #define SCZ_CEAFAR_PIO_PCIAM 0x0000030000000000UL /* pcia: memory */
178: #define SCZ_CEAFAR_PIO_PCIAI 0x0000020000000000UL /* pcia: interface */
179: #define SZC_CEAFAR_PIO_PCIBC 0x0000018000000000UL /* pcia: config / i/o */
180: #define SZC_CEAFAR_PIO_PCIBM 0x0000010000000000UL /* pcib: memory */
181: #define SZC_CEAFAR_PIO_PCIBI 0x0000000000000000UL /* pcib: interface */
182: #define SCZ_CEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */
183: #define SCZ_CEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */
184:
185: #define SCZ_PCICTRL_BUS_UNUS (1UL << 63UL) /* bus unusable */
186: #define TOM_PCICTRL_DTO_ERR (1UL << 62UL) /* pci discard timeout */
187: #define TOM_PCICTRL_DTO_INT (1UL << 61UL) /* discard intr en */
188: #define SCZ_PCICTRL_ESLCK (1UL << 51UL) /* error slot locked */
189: #define SCZ_PCICTRL_ERRSLOT (7UL << 48UL) /* error slot */
190: #define SCZ_PCICTRL_TTO_ERR (1UL << 38UL) /* pci trdy# timeout */
191: #define SCZ_PCICTRL_RTRY_ERR (1UL << 37UL) /* pci rtry# timeout */
192: #define SCZ_PCICTRL_MMU_ERR (1UL << 36UL) /* pci mmu error */
193: #define SCZ_PCICTRL_SBH_ERR (1UL << 35UL) /* pci strm hole */
194: #define SCZ_PCICTRL_SERR (1UL << 34UL) /* pci serr# sampled */
195: #define SCZ_PCICTRL_PCISPD (1UL << 33UL) /* speed (0=clk/2,1=clk) */
196: #define SCZ_PCICTRL_PTO (3UL << 24UL) /* pci timeout interval */
197: #define SCZ_PCICTRL_MMU_INT (1UL << 19UL) /* mmu intr en */
198: #define SCZ_PCICTRL_SBH_INT (1UL << 18UL) /* strm byte hole intr en */
199: #define SCZ_PCICTRL_EEN (1UL << 17UL) /* error intr en */
200: #define SCZ_PCICTRL_PARK (1UL << 16UL) /* bus parked */
201: #define SCZ_PCICTRL_PCIRST (1UL << 8UL) /* pci reset */
202: #define SCZ_PCICTRL_ARB (0x3fUL << 0UL) /* dma arb enables */
203: #define SCZ_PCICTRL_BITS "\20\277UNUS\276DTO\275DTO_INT\263ESLCK\246TTO\245RTRY\244MMU\243SBH\242SERR\241SPD\223MMU_INT\222SBH_INT\221EEN\220PARK\210PCIRST"
204:
205: #define SCZ_PCIAFSR_PMA 0x8000000000000000UL
206: #define SCZ_PCIAFSR_PTA 0x4000000000000000UL
207: #define SCZ_PCIAFSR_PRTRY 0x2000000000000000UL
208: #define SCZ_PCIAFSR_PPERR 0x1000000000000000UL
209: #define SCZ_PCIAFSR_PTTO 0x0800000000000000UL
210: #define SCZ_PCIAFSR_PUNUS 0x0400000000000000UL
211: #define SCZ_PCIAFSR_SMA 0x0200000000000000UL
212: #define SCZ_PCIAFSR_STA 0x0100000000000000UL
213: #define SCZ_PCIAFSR_SRTRY 0x0080000000000000UL
214: #define SCZ_PCIAFSR_SPERR 0x0040000000000000UL
215: #define SCZ_PCIAFSR_STTO 0x0020000000000000UL
216: #define SCZ_PCIAFSR_SUNUS 0x0010000000000000UL
217: #define SCZ_PCIAFSR_BMSK 0x000003ff00000000UL
218: #define SCZ_PCIAFSR_BLK 0x0000000080000000UL
219: #define SCZ_PCIAFSR_CFG 0x0000000040000000UL
220: #define SCZ_PCIAFSR_MEM 0x0000000020000000UL
221: #define SCZ_PCIAFSR_IO 0x0000000010000000UL
222:
223: #define SCZ_PCIAFSR_BITS "\20\277PMA\276PTA\275PRTRY\274PPERR\273PTTO\272PUNUS\271SMA\270STA\267SRTRY\266SPERR\265STTO\264SUNUS\237BLK\236CFG\235MEM\234IO"
224:
225: #define SCZ_PCIDIAG_D_BADECC (1UL << 10UL) /* disable bad ecc */
226: #define SCZ_PCIDIAG_D_BYPASS (1UL << 9UL) /* disable mmu bypass */
227: #define SCZ_PCIDIAG_D_TTO (1UL << 8UL) /* disable trdy# timeout */
228: #define SCZ_PCIDIAG_D_RTRYARB (1UL << 7UL) /* disable retry arb */
229: #define SCZ_PCIDIAG_D_RETRY (1UL << 6UL) /* disable retry lim */
230: #define SCZ_PCIDIAG_D_INTSYNC (1UL << 5UL) /* disable write sync */
231: #define SCZ_PCIDIAG_I_DMADPAR (1UL << 3UL) /* invert dma parity */
232: #define SCZ_PCIDIAG_I_PIODPAR (1UL << 2UL) /* invert pio data parity */
233: #define SCZ_PCIDIAG_I_PIOAPAR (1UL << 1UL) /* invert pio addr parity */
234:
235: #define TOM_IOMMU_ERR (1UL << 24)
236: #define TOM_IOMMU_ERR_MASK (3UL << 25)
237: #define TOM_IOMMU_PROT_ERR (0UL << 25)
238: #define TOM_IOMMU_INV_ERR (1UL << 25)
239: #define TOM_IOMMU_TO_ERR (2UL << 25)
240: #define TOM_IOMMU_ECC_ERR (3UL << 25)
241: #define TOM_IOMMU_ILLTSBTBW_ERR (1UL << 27)
242: #define TOM_IOMMU_BADVA_ERR (1UL << 28)
243:
244: #define SCZ_PBM_A_REGS (0x600000UL - 0x400000UL)
245: #define SCZ_PBM_B_REGS (0x700000UL - 0x400000UL)
246:
247: #define SCZ_UE_INO 0x30 /* uncorrectable error */
248: #define SCZ_CE_INO 0x31 /* correctable ecc error */
249: #define SCZ_PCIERR_A_INO 0x32 /* PCI A bus error */
250: #define SCZ_PCIERR_B_INO 0x33 /* PCI B bus error */
251: #define SCZ_SERR_INO 0x34 /* safari interface error */
252:
253: struct schizo_range {
254: u_int32_t cspace;
255: u_int32_t child_hi;
256: u_int32_t child_lo;
257: u_int32_t phys_hi;
258: u_int32_t phys_lo;
259: u_int32_t size_hi;
260: u_int32_t size_lo;
261: };
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