Annotation of sys/arch/sparc64/dev/sbusreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: sbusreg.h,v 1.3 2007/05/29 09:54:15 sobrado Exp $ */
2: /* $NetBSD: sbusreg.h,v 1.7 1999/06/07 05:28:03 eeh Exp $ */
3:
4: /*
5: * Copyright (c) 1996-1999 Eduardo Horvath
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: *
13: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
14: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
17: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23: * SUCH DAMAGE.
24: *
25: */
26:
27:
28: /*
29: * SBus device addresses are obtained from the FORTH PROMs. They come
30: * in `absolute' and `relative' address flavors, so we have to handle both.
31: * Relative addresses do *not* include the slot number.
32: */
33: #define SBUS_BASE 0xf8000000
34: #define SBUS_ADDR(slot, off) (SBUS_BASE + ((slot) << 25) + (off))
35: #define SBUS_ABS(a) ((unsigned)(a) >= SBUS_BASE)
36: #define SBUS_ABS_TO_SLOT(a) (((a) - SBUS_BASE) >> 25)
37: #define SBUS_ABS_TO_OFFSET(a) (((a) - SBUS_BASE) & 0x1ffffff)
38:
39: /*
40: * Sun4u SBus definitions. Here's where we deal w/the machine
41: * dependencies of sysio.
42: *
43: * SYSIO implements or is the interface to several things:
44: *
45: * o The SBus interface itself
46: * o The IOMMU
47: * o The DVMA units
48: * o The interrupt controller
49: * o The counter/timers
50: *
51: * Since it has registers to control lots of different things
52: * as well as several on-board SBus devices and external SBus
53: * slots scattered throughout its address space, it's a pain.
54: *
55: * One good point, however, is that all registers are 64-bit.
56: */
57:
58: struct sysioreg {
59: struct upareg {
60: u_int64_t upa_portid; /* UPA port ID register */ /* 1fe.0000.0000 */
61: u_int64_t upa_config; /* UPA config register */ /* 1fe.0000.0008 */
62: } sys_upa;
63:
64: u_int64_t sys_csr; /* SYSIO control/status register */ /* 1fe.0000.0010 */
65: u_int64_t pad0;
66: u_int64_t sys_ecccr; /* ECC control register */ /* 1fe.0000.0020 */
67: u_int64_t reserved; /* 1fe.0000.0028 */
68: u_int64_t sys_ue_afsr; /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */
69: u_int64_t sys_ue_afar; /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */
70: u_int64_t sys_ce_afsr; /* Correctable Error AFSR */ /* 1fe.0000.0040 */
71: u_int64_t sys_ce_afar; /* Correctable Error AFAR */ /* 1fe.0000.0048 */
72:
73: u_int64_t pad1[22];
74:
75: struct perfmon {
76: u_int64_t pm_cr; /* Performance monitor control reg */ /* 1fe.0000.0100 */
77: u_int64_t pm_count; /* Performance monitor counter reg */ /* 1fe.0000.0108 */
78: } sys_pm;
79:
80: u_int64_t pad2[990];
81:
82: struct sbusreg {
83: u_int64_t sbus_cr; /* SBus Control Register */ /* 1fe.0000.2000 */
84: u_int64_t reserved; /* 1fe.0000.2008 */
85: u_int64_t sbus_afsr; /* SBus AFSR */ /* 1fe.0000.2010 */
86: u_int64_t sbus_afar; /* SBus AFAR */ /* 1fe.0000.2018 */
87: u_int64_t sbus_config0; /* SBus Slot 0 config register */ /* 1fe.0000.2020 */
88: u_int64_t sbus_config1; /* SBus Slot 1 config register */ /* 1fe.0000.2028 */
89: u_int64_t sbus_config2; /* SBus Slot 2 config register */ /* 1fe.0000.2030 */
90: u_int64_t sbus_config3; /* SBus Slot 3 config register */ /* 1fe.0000.2038 */
91: u_int64_t sbus_config13; /* Slot 13 config register <audio> */ /* 1fe.0000.2040 */
92: u_int64_t sbus_config14; /* Slot 14 config register <macio> */ /* 1fe.0000.2048 */
93: u_int64_t sbus_config15; /* Slot 15 config register <slavio> */ /* 1fe.0000.2050 */
94: } sys_sbus;
95:
96: u_int64_t pad3[117];
97:
98: struct iommureg sys_iommu; /* 1fe.0000.2400,2410 */
99:
100: u_int64_t pad4[125];
101:
102: struct iommu_strbuf sys_strbuf; /* 1fe.0000.2800-2810 */
103:
104: u_int64_t pad5[125];
105:
106: u_int64_t sbus_slot0_int; /* SBus slot 0 interrupt map reg */ /* 1fe.0000.2c00 */
107: u_int64_t sbus_slot1_int; /* SBus slot 1 interrupt map reg */ /* 1fe.0000.2c08 */
108: u_int64_t sbus_slot2_int; /* SBus slot 2 interrupt map reg */ /* 1fe.0000.2c10 */
109: u_int64_t sbus_slot3_int; /* SBus slot 3 interrupt map reg */ /* 1fe.0000.2c18 */
110: u_int64_t intr_retry; /* interrupt retry timer reg */ /* 1fe.0000.2c20 */
111:
112: u_int64_t pad6[123];
113:
114: u_int64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.3000 */
115: u_int64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.3008 */
116: u_int64_t bpp_int_map; /* parallel interrupt map reg */ /* 1fe.0000.3010 */
117: u_int64_t audio_int_map; /* audio interrupt map reg */ /* 1fe.0000.3018 */
118: u_int64_t power_int_map; /* power fail interrupt map reg */ /* 1fe.0000.3020 */
119: u_int64_t ser_kbd_ms_int_map; /* serial/kbd/mouse interrupt map reg *//* 1fe.0000.3028 */
120: u_int64_t fd_int_map; /* floppy interrupt map reg */ /* 1fe.0000.3030 */
121: u_int64_t therm_int_map; /* thermal warn interrupt map reg */ /* 1fe.0000.3038 */
122: u_int64_t kbd_int_map; /* kbd [unused] interrupt map reg */ /* 1fe.0000.3040 */
123: u_int64_t mouse_int_map; /* mouse [unused] interrupt map reg */ /* 1fe.0000.3048 */
124: u_int64_t serial_int_map; /* second serial interrupt map reg */ /* 1fe.0000.3050 */
125: u_int64_t pad7;
126: u_int64_t timer0_int_map; /* timer 0 interrupt map reg */ /* 1fe.0000.3060 */
127: u_int64_t timer1_int_map; /* timer 1 interrupt map reg */ /* 1fe.0000.3068 */
128: u_int64_t ue_int_map; /* UE interrupt map reg */ /* 1fe.0000.3070 */
129: u_int64_t ce_int_map; /* CE interrupt map reg */ /* 1fe.0000.3078 */
130: u_int64_t sbus_async_int_map; /* SBus error interrupt map reg */ /* 1fe.0000.3080 */
131: u_int64_t pwrmgt_int_map; /* power mgmt wake interrupt map reg */ /* 1fe.0000.3088 */
132: u_int64_t upagr_int_map; /* UPA graphics interrupt map reg */ /* 1fe.0000.3090 */
133: u_int64_t reserved_int_map; /* reserved interrupt map reg */ /* 1fe.0000.3098 */
134:
135: u_int64_t pad8[108];
136:
137: /* Note: clear interrupt 0 registers are not really used */
138: u_int64_t sbus0_clr_int[8]; /* SBus slot 0 clear int regs 0..7 */ /* 1fe.0000.3400-3438 */
139: u_int64_t sbus1_clr_int[8]; /* SBus slot 1 clear int regs 0..7 */ /* 1fe.0000.3440-3478 */
140: u_int64_t sbus2_clr_int[8]; /* SBus slot 2 clear int regs 0..7 */ /* 1fe.0000.3480-34b8 */
141: u_int64_t sbus3_clr_int[8]; /* SBus slot 3 clear int regs 0..7 */ /* 1fe.0000.34c0-34f8 */
142:
143: u_int64_t pad9[96];
144:
145: u_int64_t scsi_clr_int; /* SCSI clear int reg */ /* 1fe.0000.3800 */
146: u_int64_t ether_clr_int; /* ethernet clear int reg */ /* 1fe.0000.3808 */
147: u_int64_t bpp_clr_int; /* parallel clear int reg */ /* 1fe.0000.3810 */
148: u_int64_t audio_clr_int; /* audio clear int reg */ /* 1fe.0000.3818 */
149: u_int64_t power_clr_int; /* power fail clear int reg */ /* 1fe.0000.3820 */
150: u_int64_t ser_kb_ms_clr_int; /* serial/kbd/mouse clear int reg */ /* 1fe.0000.3828 */
151: u_int64_t fd_clr_int; /* floppy clear int reg */ /* 1fe.0000.3830 */
152: u_int64_t therm_clr_int; /* thermal warn clear int reg */ /* 1fe.0000.3838 */
153: u_int64_t kbd_clr_int; /* kbd [unused] clear int reg */ /* 1fe.0000.3840 */
154: u_int64_t mouse_clr_int; /* mouse [unused] clear int reg */ /* 1fe.0000.3848 */
155: u_int64_t serial_clr_int; /* second serial clear int reg */ /* 1fe.0000.3850 */
156: u_int64_t pad10;
157: u_int64_t timer0_clr_int; /* timer 0 clear int reg */ /* 1fe.0000.3860 */
158: u_int64_t timer1_clr_int; /* timer 1 clear int reg */ /* 1fe.0000.3868 */
159: u_int64_t ue_clr_int; /* UE clear int reg */ /* 1fe.0000.3870 */
160: u_int64_t ce_clr_int; /* CE clear int reg */ /* 1fe.0000.3878 */
161: u_int64_t sbus_clr_async_int; /* SBus error clr interrupt reg */ /* 1fe.0000.3880 */
162: u_int64_t pwrmgt_clr_int; /* power mgmt wake clr interrupt reg */ /* 1fe.0000.3888 */
163:
164: u_int64_t pad11[110];
165:
166: struct timer_counter {
167: u_int64_t tc_count; /* timer/counter 0/1 count register */ /* ife.0000.3c00,3c10 */
168: u_int64_t tc_limit; /* timer/counter 0/1 limit register */ /* ife.0000.3c08,3c18 */
169: } tc[2];
170:
171: u_int64_t pad12[252];
172:
173: u_int64_t sys_svadiag; /* SBus virtual addr diag reg */ /* 1fe.0000.4400 */
174:
175: u_int64_t pad13[31];
176:
177: u_int64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.4500-457f */
178: u_int64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.4580-45ff */
179: u_int64_t tlb_data_diag[32]; /* TLB data RAM diag */ /* 1fe.0000.4600-46ff */
180:
181: u_int64_t pad14[32];
182:
183: u_int64_t sbus_int_diag; /* SBus int state diag reg */ /* 1fe.0000.4800 */
184: u_int64_t obio_int_diag; /* OBIO and misc int state diag reg */ /* 1fe.0000.4808 */
185:
186: u_int64_t pad15[254];
187:
188: u_int64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.5000-53f8 */
189: u_int64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.5400-57f8 */
190: u_int64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.5800-5878 */
191: u_int64_t pad16[16];
192: u_int64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.5900-5978 */
193: };
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