Annotation of sys/arch/sparc64/dev/psychoreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: psychoreg.h,v 1.11 2006/02/06 17:19:31 jmc Exp $ */
! 2: /* $NetBSD: psychoreg.h,v 1.6.4.2 2001/09/13 01:14:40 thorpej Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1998, 1999 Eduardo E. Horvath
! 6: * Copyright (c) 1999 Matthew R. Green
! 7: * All rights reserved.
! 8: *
! 9: * Redistribution and use in source and binary forms, with or without
! 10: * modification, are permitted provided that the following conditions
! 11: * are met:
! 12: * 1. Redistributions of source code must retain the above copyright
! 13: * notice, this list of conditions and the following disclaimer.
! 14: * 2. Redistributions in binary form must reproduce the above copyright
! 15: * notice, this list of conditions and the following disclaimer in the
! 16: * documentation and/or other materials provided with the distribution.
! 17: * 3. The name of the author may not be used to endorse or promote products
! 18: * derived from this software without specific prior written permission.
! 19: *
! 20: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 21: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 22: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 23: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 24: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! 25: * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
! 26: * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
! 27: * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
! 28: * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 29: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 30: * SUCH DAMAGE.
! 31: */
! 32: #ifndef _SPARC64_DEV_PSYCHOREG_H_
! 33: #define _SPARC64_DEV_PSYCHOREG_H_
! 34:
! 35: /*
! 36: * Sun4u PCI definitions. Here's where we deal w/the machine
! 37: * dependencies of psycho and the PCI controller on the UltraIIi.
! 38: *
! 39: * All PCI registers are bit-swapped, however they are not byte-swapped.
! 40: * This means that they must be accessed using little-endian access modes,
! 41: * either map the pages little-endian or use little-endian ASIs.
! 42: *
! 43: * PSYCHO implements two PCI buses, A and B.
! 44: */
! 45:
! 46: struct psychoreg {
! 47: struct upareg {
! 48: u_int64_t upa_portid; /* UPA port ID register */ /* 1fe.0000.0000 */
! 49: u_int64_t upa_config; /* UPA config register */ /* 1fe.0000.0008 */
! 50: } sys_upa;
! 51:
! 52: u_int64_t psy_csr; /* PSYCHO control/status register */ /* 1fe.0000.0010 */
! 53: /*
! 54: * 63 59 55 50 45 4 3 2 1 0
! 55: * +------+------+------+------+--//---+--------+-------+-----+------+
! 56: * | IMPL | VERS | MID | IGN | xxx | APCKEN | APERR | IAP | MODE |
! 57: * +------+------+------+------+--//---+--------+-------+-----+------+
! 58: *
! 59: */
! 60: #define PSYCHO_GCSR_IMPL(csr) ((u_int)(((csr) >> 60) & 0xf))
! 61: #define PSYCHO_GCSR_VERS(csr) ((u_int)(((csr) >> 56) & 0xf))
! 62: #define PSYCHO_GCSR_MID(csr) ((u_int)(((csr) >> 51) & 0x1f))
! 63: #define PSYCHO_GCSR_IGN(csr) ((u_int)(((csr) >> 46) & 0x1f))
! 64: #define PSYCHO_CSR_APCKEN 8 /* UPA addr parity check enable */
! 65: #define PSYCHO_CSR_APERR 4 /* UPA addr parity error */
! 66: #define PSYCHO_CSR_IAP 2 /* invert UPA address parity */
! 67: #define PSYCHO_CSR_MODE 1 /* UPA/PCI handshake */
! 68:
! 69: u_int64_t pad0;
! 70: u_int64_t psy_ecccr; /* ECC control register */ /* 1fe.0000.0020 */
! 71: u_int64_t reserved; /* 1fe.0000.0028 */
! 72: u_int64_t psy_ue_afsr; /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */
! 73: u_int64_t psy_ue_afar; /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */
! 74: u_int64_t psy_ce_afsr; /* Correctable Error AFSR */ /* 1fe.0000.0040 */
! 75: u_int64_t psy_ce_afar; /* Correctable Error AFAR */ /* 1fe.0000.0048 */
! 76:
! 77: u_int64_t pad1[22];
! 78:
! 79: struct perfmon {
! 80: u_int64_t pm_cr; /* Performance monitor control reg */ /* 1fe.0000.0100 */
! 81: u_int64_t pm_count; /* Performance monitor counter reg */ /* 1fe.0000.0108 */
! 82: } psy_pm;
! 83:
! 84: u_int64_t pad2[30];
! 85:
! 86: struct iommureg psy_iommu; /* 1fe.0000.0200,0210 */
! 87:
! 88: u_int64_t pad3[317];
! 89:
! 90: u_int64_t pcia_slot0_int; /* PCI bus a slot 0 irq map reg */ /* 1fe.0000.0c00 */
! 91: u_int64_t pcia_slot1_int; /* PCI bus a slot 1 irq map reg */ /* 1fe.0000.0c08 */
! 92: u_int64_t pcia_slot2_int; /* PCI bus a slot 2 irq map reg (IIi)*/ /* 1fe.0000.0c10 */
! 93: u_int64_t pcia_slot3_int; /* PCI bus a slot 3 irq map reg (IIi)*/ /* 1fe.0000.0c18 */
! 94: u_int64_t pcib_slot0_int; /* PCI bus b slot 0 irq map reg */ /* 1fe.0000.0c20 */
! 95: u_int64_t pcib_slot1_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c28 */
! 96: u_int64_t pcib_slot2_int; /* PCI bus b slot 2 irq map reg */ /* 1fe.0000.0c30 */
! 97: u_int64_t pcib_slot3_int; /* PCI bus b slot 3 irq map reg */ /* 1fe.0000.0c38 */
! 98:
! 99: u_int64_t pad4[120];
! 100:
! 101: u_int64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.1000 */
! 102: u_int64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.1008 */
! 103: u_int64_t bpp_int_map; /* parallel interrupt map reg */ /* 1fe.0000.1010 */
! 104: u_int64_t audior_int_map; /* audio record interrupt map reg */ /* 1fe.0000.1018 */
! 105: u_int64_t audiop_int_map; /* audio playback interrupt map reg */ /* 1fe.0000.1020 */
! 106: u_int64_t power_int_map; /* power fail interrupt map reg */ /* 1fe.0000.1028 */
! 107: u_int64_t ser_kbd_ms_int_map; /* serial/kbd/mouse interrupt map reg *//* 1fe.0000.1030 */
! 108: u_int64_t fd_int_map; /* floppy interrupt map reg */ /* 1fe.0000.1038 */
! 109: u_int64_t spare_int_map; /* spare interrupt map reg */ /* 1fe.0000.1040 */
! 110: u_int64_t kbd_int_map; /* kbd [unused] interrupt map reg */ /* 1fe.0000.1048 */
! 111: u_int64_t mouse_int_map; /* mouse [unused] interrupt map reg */ /* 1fe.0000.1050 */
! 112: u_int64_t serial_int_map; /* second serial interrupt map reg */ /* 1fe.0000.1058 */
! 113: u_int64_t timer0_int_map; /* timer 0 interrupt map reg */ /* 1fe.0000.1060 */
! 114: u_int64_t timer1_int_map; /* timer 1 interrupt map reg */ /* 1fe.0000.1068 */
! 115: u_int64_t ue_int_map; /* UE interrupt map reg */ /* 1fe.0000.1070 */
! 116: u_int64_t ce_int_map; /* CE interrupt map reg */ /* 1fe.0000.1078 */
! 117: u_int64_t pciaerr_int_map; /* PCI bus a error interrupt map reg */ /* 1fe.0000.1080 */
! 118: u_int64_t pciberr_int_map; /* PCI bus b error interrupt map reg */ /* 1fe.0000.1088 */
! 119: u_int64_t pwrmgt_int_map; /* power mgmt wake interrupt map reg */ /* 1fe.0000.1090 */
! 120: u_int64_t ffb0_int_map; /* FFB0 graphics interrupt map reg */ /* 1fe.0000.1098 */
! 121: u_int64_t ffb1_int_map; /* FFB1 graphics interrupt map reg */ /* 1fe.0000.10a0 */
! 122:
! 123: u_int64_t pad5[107];
! 124:
! 125: /* Note: clear interrupt 0 registers are not really used */
! 126: u_int64_t pcia0_clr_int[4]; /* PCI a slot 0 clear int regs 0..7 */ /* 1fe.0000.1400-1418 */
! 127: u_int64_t pcia1_clr_int[4]; /* PCI a slot 1 clear int regs 0..7 */ /* 1fe.0000.1420-1438 */
! 128: u_int64_t pcia2_clr_int[4]; /* PCI a slot 2 clear int regs 0..7 */ /* 1fe.0000.1440-1458 */
! 129: u_int64_t pcia3_clr_int[4]; /* PCI a slot 3 clear int regs 0..7 */ /* 1fe.0000.1480-1478 */
! 130: u_int64_t pcib0_clr_int[4]; /* PCI b slot 0 clear int regs 0..7 */ /* 1fe.0000.1480-1498 */
! 131: u_int64_t pcib1_clr_int[4]; /* PCI b slot 1 clear int regs 0..7 */ /* 1fe.0000.14a0-14b8 */
! 132: u_int64_t pcib2_clr_int[4]; /* PCI b slot 2 clear int regs 0..7 */ /* 1fe.0000.14c0-14d8 */
! 133: u_int64_t pcib3_clr_int[4]; /* PCI b slot 3 clear int regs 0..7 */ /* 1fe.0000.14d0-14f8 */
! 134:
! 135: u_int64_t pad6[96];
! 136:
! 137: u_int64_t scsi_clr_int; /* SCSI clear int reg */ /* 1fe.0000.1800 */
! 138: u_int64_t ether_clr_int; /* ethernet clear int reg */ /* 1fe.0000.1808 */
! 139: u_int64_t bpp_clr_int; /* parallel clear int reg */ /* 1fe.0000.1810 */
! 140: u_int64_t audior_clr_int; /* audio record clear int reg */ /* 1fe.0000.1818 */
! 141: u_int64_t audiop_clr_int; /* audio playback clear int reg */ /* 1fe.0000.1820 */
! 142: u_int64_t power_clr_int; /* power fail clear int reg */ /* 1fe.0000.1828 */
! 143: u_int64_t ser_kb_ms_clr_int; /* serial/kbd/mouse clear int reg */ /* 1fe.0000.1830 */
! 144: u_int64_t fd_clr_int; /* floppy clear int reg */ /* 1fe.0000.1838 */
! 145: u_int64_t spare_clr_int; /* spare clear int reg */ /* 1fe.0000.1840 */
! 146: u_int64_t kbd_clr_int; /* kbd [unused] clear int reg */ /* 1fe.0000.1848 */
! 147: u_int64_t mouse_clr_int; /* mouse [unused] clear int reg */ /* 1fe.0000.1850 */
! 148: u_int64_t serial_clr_int; /* second serial clear int reg */ /* 1fe.0000.1858 */
! 149: u_int64_t timer0_clr_int; /* timer 0 clear int reg */ /* 1fe.0000.1860 */
! 150: u_int64_t timer1_clr_int; /* timer 1 clear int reg */ /* 1fe.0000.1868 */
! 151: u_int64_t ue_clr_int; /* UE clear int reg */ /* 1fe.0000.1870 */
! 152: u_int64_t ce_clr_int; /* CE clear int reg */ /* 1fe.0000.1878 */
! 153: u_int64_t pciaerr_clr_int; /* PCI bus a error clear int reg */ /* 1fe.0000.1880 */
! 154: u_int64_t pciberr_clr_int; /* PCI bus b error clear int reg */ /* 1fe.0000.1888 */
! 155: u_int64_t pwrmgt_clr_int; /* power mgmt wake clr interrupt reg */ /* 1fe.0000.1890 */
! 156:
! 157: u_int64_t pad7[45];
! 158:
! 159: u_int64_t intr_retry_timer; /* interrupt retry timer */ /* 1fe.0000.1a00 */
! 160:
! 161: u_int64_t pad8[63];
! 162:
! 163: struct timer_counter {
! 164: u_int64_t tc_count; /* timer/counter 0/1 count register */ /* 1fe.0000.1c00,1c10 */
! 165: u_int64_t tc_limit; /* timer/counter 0/1 limit register */ /* 1fe.0000.1c08,1c18 */
! 166: } tc[2];
! 167:
! 168: u_int64_t pci_dma_write_sync; /* PCI DMA write sync register (IIi) */ /* 1fe.0000.1c20 */
! 169:
! 170: u_int64_t pad9[123];
! 171:
! 172: struct pci_ctl {
! 173: u_int64_t pci_csr; /* PCI a/b control/status register */ /* 1fe.0000.2000,4000 */
! 174: u_int64_t pad10;
! 175: u_int64_t pci_afsr; /* PCI a/b AFSR register */ /* 1fe.0000.2010,4010 */
! 176: u_int64_t pci_afar; /* PCI a/b AFAR register */ /* 1fe.0000.2018,4018 */
! 177: u_int64_t pci_diag; /* PCI a/b diagnostic register */ /* 1fe.0000.2020,4020 */
! 178: u_int64_t pci_tasr; /* PCI target address space reg (IIi)*/ /* 1fe.0000.2028,4028 */
! 179:
! 180: u_int64_t pad11[250];
! 181:
! 182: /* This is really the IOMMU's, not the PCI bus's */
! 183: struct iommu_strbuf pci_strbuf; /* 1fe.0000.2800-210 */
! 184: #define psy_iommu_strbuf psy_pcictl[0].pci_strbuf
! 185:
! 186: u_int64_t pad12[765];
! 187: } psy_pcictl[2]; /* For PCI a and b */
! 188:
! 189: /* NB: FFB0 and FFB1 intr map regs also appear at 1fe.0000.6000 and 1fe.0000.8000 respectively */
! 190: u_int64_t pad13[2048];
! 191:
! 192: u_int64_t dma_scb_diag0; /* DMA scoreboard diag reg 0 */ /* 1fe.0000.a000 */
! 193: u_int64_t dma_scb_diag1; /* DMA scoreboard diag reg 1 */ /* 1fe.0000.a008 */
! 194:
! 195: u_int64_t pad14[126];
! 196:
! 197: u_int64_t iommu_svadiag; /* IOMMU virtual addr diag reg */ /* 1fe.0000.a400 */
! 198: u_int64_t iommu_tlb_comp_diag; /* IOMMU TLB tag compare diag reg */ /* 1fe.0000.a408 */
! 199:
! 200: u_int64_t pad15[30];
! 201:
! 202: u_int64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.a500-a578 */
! 203: u_int64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.a580-a5f8 */
! 204: u_int64_t tlb_data_diag[16]; /* TLB data RAM diag */ /* 1fe.0000.a600-a678 */
! 205:
! 206: u_int64_t pad16[48];
! 207:
! 208: u_int64_t pci_int_diag; /* PCI int state diag reg */ /* 1fe.0000.a800 */
! 209: u_int64_t obio_int_diag; /* OBIO and misc int state diag reg */ /* 1fe.0000.a808 */
! 210:
! 211: u_int64_t pad17[254];
! 212:
! 213: struct strbuf_diag {
! 214: u_int64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.b000-b3f8 */
! 215: u_int64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.b400-b7f8 */
! 216: u_int64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.b800-b878 */
! 217: u_int64_t pad18[16];
! 218: u_int64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.b900-b978 */
! 219: u_int64_t pad19[208];
! 220: } psy_strbufdiag[2]; /* For PCI a and b */
! 221:
! 222: /*
! 223: * Here is the rest of the map, which we're not specifying:
! 224: *
! 225: * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space
! 226: * 1fe.0100.0000 - 1fe.0100.00ff PCI B configuration header
! 227: * 1fe.0101.0000 - 1fe.0101.00ff PCI A configuration header
! 228: * 1fe.0200.0000 - 1fe.0200.ffff PCI A I/O space
! 229: * 1fe.0201.0000 - 1fe.0201.ffff PCI B I/O space
! 230: * 1ff.0000.0000 - 1ff.7fff.ffff PCI A memory space
! 231: * 1ff.8000.0000 - 1ff.ffff.ffff PCI B memory space
! 232: *
! 233: * NB: config and I/O space can use 1-4 byte accesses, not 8 byte
! 234: * accesses. Memory space can use any sized accesses.
! 235: *
! 236: * Note that the SUNW,sabre/SUNW,simba combinations found on the
! 237: * Ultra5 and Ultra10 machines uses slightly differrent addresses
! 238: * than the above. This is mostly due to the fact that the APB is
! 239: * a multi-function PCI device with two PCI bridges, and the U2P is
! 240: * two separate PCI bridges. It uses the same PCI configuration
! 241: * space, though the configuration header for each PCI bus is
! 242: * located differently due to the SUNW,simba PCI busses being
! 243: * function 0 and function 1 of the APB, whereas the psycho's are
! 244: * each their own PCI device. The I/O and memory spaces are each
! 245: * split into 8 equally sized areas (8x2MB blocks for I/O space,
! 246: * and 8x512MB blocks for memory space). These are allocated in to
! 247: * either PCI A or PCI B, or neither in the APB's `I/O Address Map
! 248: * Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf)
! 249: * registers of each simba. We must ensure that both of the
! 250: * following are correct (the prom should do this for us):
! 251: *
! 252: * (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0
! 253: *
! 254: * (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0
! 255: *
! 256: * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space
! 257: * 1fe.0100.0800 - 1fe.0100.08ff PCI B configuration header
! 258: * 1fe.0100.0900 - 1fe.0100.09ff PCI A configuration header
! 259: * 1fe.0200.0000 - 1fe.02ff.ffff PCI I/O space (divided)
! 260: * 1ff.0000.0000 - 1ff.ffff.ffff PCI memory space (divided)
! 261: */
! 262: };
! 263:
! 264: /* what the bits mean! */
! 265:
! 266: /* uncorrectable error fault status */
! 267: #define PSY_UEAFSR_PDRD 0x4000000000000000 /* primary pci dma read */
! 268: #define PSY_UEAFSR_PDWR 0x2000000000000000 /* primary pci dma write */
! 269: #define PSY_UEAFSR_SDRD 0x0800000000000000 /* secondary pci dma read */
! 270: #define PSY_UEAFSR_SDWR 0x0400000000000000 /* secondary pci dma write */
! 271: #define PSY_UEAFSR_SDTE 0x0200000000000000 /* secondary dma translation error */
! 272: #define PSY_UEAFSR_PDTE 0x0100000000000000 /* primary dma translation error */
! 273: #define PSY_UEAFSR_MASK 0x0000ffff00000000 /* byte mask */
! 274: #define PSY_UEAFSR_OFF 0x00000000e0000000 /* offset (afar [5:3]) */
! 275: #define PSY_UEAFSR_BLK 0x0000000000800000 /* block operation */
! 276:
! 277: /* correctable error fault status */
! 278: #define PSY_CEAFSR_PDRD 0x4000000000000000 /* primary pci dma read */
! 279: #define PSY_CEAFSR_PDWR 0x2000000000000000 /* primary pci dma write */
! 280: #define PSY_CEAFSR_SDRD 0x0800000000000000 /* secondary pci dma read */
! 281: #define PSY_CEAFSR_SDWR 0x0400000000000000 /* secondary pci dma write */
! 282: #define PSY_CEAFSR_SYND 0x00ff000000000000 /* ecc syndrome */
! 283: #define PSY_CEAFSR_MASK 0x0000ffff00000000 /* byte mask */
! 284: #define PSY_CEAFSR_OFF 0x00000000e0000000 /* offset (afar [5:3]) */
! 285: #define PSY_CEAFSR_BLK 0x0000000000800000 /* block operation */
! 286:
! 287: /* PCI [a|b] control/status register */
! 288: /* note that the sabre only has one set of PCI control/status registers */
! 289: #define PCICTL_MRLM 0x0000001000000000 /* Memory Read Line/Multiple */
! 290: #define PCICTL_SERR 0x0000000400000000 /* SERR asserted; W1C */
! 291: #define PCICTL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */
! 292: #define PCICTL_CPU_PRIO 0x0000000000100000 /* PCI arbitration parking */
! 293: #define PCICTL_ARB_PRIO 0x00000000000f0000 /* PCI arbitration parking */
! 294: #define PCICTL_ERRINTEN 0x0000000000000100 /* PCI error interrupt enable */
! 295: #define PCICTL_RTRYWAIT 0x0000000000000080 /* PCI error interrupt enable */
! 296: #define PCICTL_4ENABLE 0x000000000000000f /* enable 4 PCI slots */
! 297: #define PCICTL_6ENABLE 0x000000000000003f /* enable 6 PCI slots */
! 298:
! 299: /* PCI [a|b] afsr */
! 300: #define PSY_PCIAFSR_PMA 0x8000000000000000 /* primary master abort */
! 301: #define PSY_PCIAFSR_PTA 0x4000000000000000 /* primary target abort */
! 302: #define PSY_PCIAFSR_PTRY 0x2000000000000000 /* primary excessive retry */
! 303: #define PSY_PCIAFSR_PPERR 0x1000000000000000 /* primary parity error */
! 304: #define PSY_PCIAFSR_SMA 0x0800000000000000 /* secondary master abort */
! 305: #define PSY_PCIAFSR_STA 0x0400000000000000 /* secondary target abort */
! 306: #define PSY_PCIAFSR_STRY 0x0200000000000000 /* secondary excessive retry */
! 307: #define PSY_PCIAFSR_SPERR 0x0100000000000000 /* secondary parity error */
! 308: #define PSY_PCIAFSR_RESV1 0x00ff000000000000 /* reserved */
! 309: #define PSY_PCIAFSR_BMSK 0x0000ffff00000000 /* byte mask of transfer */
! 310: #define PSY_PCIAFSR_BLK 0x0000000080000000 /* block operation */
! 311: #define PSY_PCIAFSR_RESV2 0x0000000040000000 /* reserved */
! 312: #define PSY_PCIAFSR_MID 0x000000003e000000 /* mid causing error */
! 313: #define PSY_PCIAFSR_RESV3 0x0000000001ffffff /* reserved */
! 314:
! 315: /* performance counter control */
! 316: #define PSY_PMCR_CLR1 0x0000000000008000 /* clear cnt 1 */
! 317: #define PSY_PMCR_SEL1 0x0000000000001f00 /* set cnt 1 src */
! 318: #define PSY_PMCR_CLR0 0x0000000000000080 /* clear cnt 0 */
! 319: #define PSY_PMCR_SEL0 0x000000000000001f /* set cnt 0 src */
! 320:
! 321: #define PSY_PMCRSEL_SDVRA 0x0000000000000000 /* stream dvma read, A */
! 322: #define PSY_PMCRSEL_SDVWA 0x0000000000000001 /* stream dvma write, A */
! 323: #define PSY_PMCRSEL_CDVRA 0x0000000000000002 /* consist dvma read, A */
! 324: #define PSY_PMCRSEL_CDVWA 0x0000000000000003 /* consist dvma write, A */
! 325: #define PSY_PMCRSEL_SBMA 0x0000000000000004 /* stream buf miss, A */
! 326: #define PSY_PMCRSEL_DVA 0x0000000000000005 /* dvma cycles, A */
! 327: #define PSY_PMCRSEL_DVWA 0x0000000000000006 /* dvma words, A */
! 328: #define PSY_PMCRSEL_PIOA 0x0000000000000007 /* pio cycles, A */
! 329: #define PSY_PMCRSEL_SDVRB 0x0000000000000008 /* stream dvma read, B */
! 330: #define PSY_PMCRSEL_SDVWB 0x0000000000000009 /* stream dvma write, B */
! 331: #define PSY_PMCRSEL_CDVRB 0x000000000000000a /* consist dvma read, B */
! 332: #define PSY_PMCRSEL_CDVWB 0x000000000000000b /* consist dvma write, B */
! 333: #define PSY_PMCRSEL_SBMB 0x000000000000000c /* stream buf miss, B */
! 334: #define PSY_PMCRSEL_DVB 0x000000000000000d /* dvma cycles, B */
! 335: #define PSY_PMCRSEL_DVWB 0x000000000000000e /* dvma words, B */
! 336: #define PSY_PMCRSEL_PIOB 0x000000000000000f /* pio cycles, B */
! 337: #define PSY_PMCRSEL_TLBMISS 0x0000000000000010 /* tlb misses */
! 338: #define PSY_PMCRSEL_NINTRS 0x0000000000000011 /* interrupts */
! 339: #define PSY_PMCRSEL_INACK 0x0000000000000012 /* intr nacks */
! 340: #define PSY_PMCRSEL_PIOR 0x0000000000000013 /* pio read xfers */
! 341: #define PSY_PMCRSEL_PIOW 0x0000000000000014 /* pio write xfers */
! 342: #define PSY_PMCRSEL_MERGE 0x0000000000000015 /* merge buffer xacts */
! 343: #define PSY_PMCRSEL_TBLA 0x0000000000000016 /* tbl walk retries, A */
! 344: #define PSY_PMCRSEL_STCA 0x0000000000000017 /* stc retries, A */
! 345: #define PSY_PMCRSEL_TBLB 0x0000000000000018 /* tbl walk retries, B */
! 346: #define PSY_PMCRSEL_STCB 0x0000000000000019 /* stc retries, B */
! 347:
! 348: /*
! 349: * these are the PROM structures we grovel
! 350: */
! 351:
! 352: /*
! 353: * For the physical addresses split into 3 32 bit values, we deocde
! 354: * them like the following (IEEE1275 PCI Bus binding 2.0, 2.2.1.1
! 355: * Numerical Representation):
! 356: *
! 357: * phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
! 358: * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
! 359: * phys.lo cell: llllllll llllllll llllllll llllllll
! 360: *
! 361: * where these bits affect the address' properties:
! 362: * n not-relocatable
! 363: * p prefetchable
! 364: * t aliased (non-relocatable IO), below 1MB (memory) or
! 365: * below 64KB (reloc. IO)
! 366: * ss address space code:
! 367: * 00 - configuration space
! 368: * 01 - I/O space
! 369: * 10 - 32 bit memory space
! 370: * 11 - 64 bit memory space
! 371: * bb..bb 8 bit bus number
! 372: * ddddd 5 bit device number
! 373: * fff 3 bit function number
! 374: * rr..rr 8 bit register number
! 375: * hh..hh 32 bit unsigned value
! 376: * ll..ll 32 bit unsigned value
! 377: * the values of hh..hh and ll..ll are combined to form a larger number.
! 378: *
! 379: * For config space, we don't have to do much special. For I/O space,
! 380: * hh..hh must be zero, and if n == 0 ll..ll is the offset from the
! 381: * start of I/O space, otherwise ll..ll is the I/O space. For memory
! 382: * space, hh..hh must be zero for the 32 bit space, and is the high 32
! 383: * bits in 64 bit space, with ll..ll being the low 32 bits in both cases,
! 384: * with offset handling being driver via `n == 0' as for I/O space.
! 385: */
! 386:
! 387: /* commonly used */
! 388: #define TAG2BUS(tag) ((tag) >> 16) & 0xff;
! 389: #define TAG2DEV(tag) ((tag) >> 11) & 0x1f;
! 390: #define TAG2FN(tag) ((tag) >> 8) & 0x7;
! 391:
! 392: struct psycho_registers {
! 393: u_int32_t phys_hi;
! 394: u_int32_t phys_mid;
! 395: u_int32_t phys_lo;
! 396: u_int32_t size_hi;
! 397: u_int32_t size_lo;
! 398: };
! 399:
! 400: struct psycho_ranges {
! 401: u_int32_t cspace;
! 402: u_int32_t child_hi;
! 403: u_int32_t child_lo;
! 404: u_int32_t phys_hi;
! 405: u_int32_t phys_lo;
! 406: u_int32_t size_hi;
! 407: u_int32_t size_lo;
! 408: };
! 409:
! 410: struct psycho_interrupt_map {
! 411: u_int32_t phys_hi;
! 412: u_int32_t phys_mid;
! 413: u_int32_t phys_lo;
! 414: u_int32_t intr;
! 415: int32_t child_node;
! 416: u_int32_t child_intr;
! 417: };
! 418:
! 419: struct psycho_interrupt_map_mask {
! 420: u_int32_t phys_hi;
! 421: u_int32_t phys_mid;
! 422: u_int32_t phys_lo;
! 423: u_int32_t intr;
! 424: };
! 425:
! 426: #endif /* _SPARC64_DEV_PSYCHOREG_H_ */
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