Annotation of sys/arch/sparc64/dev/iommureg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: iommureg.h,v 1.15 2007/05/29 09:53:59 sobrado Exp $ */
! 2: /* $NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1992, 1993
! 6: * The Regents of the University of California. All rights reserved.
! 7: *
! 8: * This software was developed by the Computer Systems Engineering group
! 9: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
! 10: * contributed to Berkeley.
! 11: *
! 12: * All advertising materials mentioning features or use of this software
! 13: * must display the following acknowledgement:
! 14: * This product includes software developed by the University of
! 15: * California, Lawrence Berkeley Laboratory.
! 16: *
! 17: * Redistribution and use in source and binary forms, with or without
! 18: * modification, are permitted provided that the following conditions
! 19: * are met:
! 20: * 1. Redistributions of source code must retain the above copyright
! 21: * notice, this list of conditions and the following disclaimer.
! 22: * 2. Redistributions in binary form must reproduce the above copyright
! 23: * notice, this list of conditions and the following disclaimer in the
! 24: * documentation and/or other materials provided with the distribution.
! 25: * 3. Neither the name of the University nor the names of its contributors
! 26: * may be used to endorse or promote products derived from this software
! 27: * without specific prior written permission.
! 28: *
! 29: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 30: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 31: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 32: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 33: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 37: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 38: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 39: * SUCH DAMAGE.
! 40: *
! 41: * @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
! 42: */
! 43:
! 44: #ifndef _SPARC64_DEV_IOMMUREG_H_
! 45: #define _SPARC64_DEV_IOMMUREG_H_
! 46:
! 47: /*
! 48: * UltraSPARC IOMMU registers, common to both the sbus and PCI
! 49: * controllers.
! 50: */
! 51:
! 52: /* iommmu registers */
! 53: struct iommureg {
! 54: volatile u_int64_t iommu_cr; /* IOMMU control register */
! 55: volatile u_int64_t iommu_tsb; /* IOMMU TSB base register */
! 56: volatile u_int64_t iommu_flush; /* IOMMU flush register */
! 57: };
! 58:
! 59: /* streaming buffer registers */
! 60: struct iommu_strbuf {
! 61: volatile u_int64_t strbuf_ctl; /* streaming buffer control reg */
! 62: volatile u_int64_t strbuf_pgflush; /* streaming buffer page flush */
! 63: volatile u_int64_t strbuf_flushsync;/* streaming buffer flush sync */
! 64: };
! 65:
! 66: #define IOMMUREG(x) (offsetof(struct iommureg, x))
! 67: #define STRBUFREG(x) (offsetof(struct iommu_strbuf, x))
! 68:
! 69: /* streaming buffer control register */
! 70: #define STRBUF_EN 0x000000000000000001LL
! 71: #define STRBUF_D 0x000000000000000002LL
! 72:
! 73: /* control register bits */
! 74: #define IOMMUCR_TSB1K 0x000000000000000000LL /* Nummber of entries in IOTSB */
! 75: #define IOMMUCR_TSB2K 0x000000000000010000LL
! 76: #define IOMMUCR_TSB4K 0x000000000000020000LL
! 77: #define IOMMUCR_TSB8K 0x000000000000030000LL
! 78: #define IOMMUCR_TSB16K 0x000000000000040000LL
! 79: #define IOMMUCR_TSB32K 0x000000000000050000LL
! 80: #define IOMMUCR_TSB64K 0x000000000000060000LL
! 81: #define IOMMUCR_TSB128K 0x000000000000070000LL
! 82: #define IOMMUCR_TSBMASK 0xfffffffffffff8ffffLL /* Mask for above */
! 83: #define IOMMUCR_8KPG 0x000000000000000000LL /* 8K iommu page size */
! 84: #define IOMMUCR_64KPG 0x000000000000000004LL /* 64K iommu page size */
! 85: #define IOMMUCR_DE 0x000000000000000002LL /* Diag enable */
! 86: #define IOMMUCR_EN 0x000000000000000001LL /* Enable IOMMU */
! 87:
! 88: /*
! 89: * IOMMU stuff
! 90: */
! 91: #define IOTTE_V 0x8000000000000000LL /* Entry valid */
! 92: #define IOTTE_64K 0x2000000000000000LL /* 8K or 64K page? */
! 93: #define IOTTE_8K 0x0000000000000000LL
! 94: #define IOTTE_STREAM 0x1000000000000000LL /* Is page streamable? */
! 95: #define IOTTE_LOCAL 0x0800000000000000LL /* Accesses to same bus segment? */
! 96: #define IOTTE_CONTEXT 0x07ff800000000000LL /* context number */
! 97: #define IOTTE_PAMASK 0x000007ffffffe000LL /* Let's assume this is correct (bits 42..13) */
! 98: #define IOTTE_C 0x0000000000000010LL /* Accesses to cacheable space */
! 99: #define IOTTE_W 0x0000000000000002LL /* Writeable */
! 100: #define IOTTE_SOFTWARE 0x0000000000001f80LL /* For software use (bits 12..7) */
! 101:
! 102:
! 103: /*
! 104: * On sun4u each bus controller has a separate IOMMU. The IOMMU has
! 105: * a TSB which must be page aligned and physically contiguous. Mappings
! 106: * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility
! 107: * with the CPU's MMU.
! 108: *
! 109: * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the
! 110: * following size segments:
! 111: *
! 112: * VA size VA base TSB size tsbsize
! 113: * -------- -------- --------- -------
! 114: * 8MB ff800000 8K 0
! 115: * 16MB ff000000 16K 1
! 116: * 32MB fe000000 32K 2
! 117: * 64MB fc000000 64K 3
! 118: * 128MB f8000000 128K 4
! 119: * 256MB f0000000 256K 5
! 120: * 512MB e0000000 512K 6
! 121: * 1GB c0000000 1MB 7
! 122: *
! 123: * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use
! 124: * this scheme to determine the IOVA base address. Instead, bits 31-29 are
! 125: * used to check against the Target Address Space register in the IIi and
! 126: * the IOMMU is used if they hit. God knows what goes on in the IIe.
! 127: *
! 128: */
! 129:
! 130:
! 131: #define IOTSB_VEND 0xffffffffU
! 132: #define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz)+10+PGSHIFT))
! 133: #define IOTSB_VSIZE(sz) (u_int)(1 << ((sz)+10+PGSHIFT))
! 134:
! 135: #define MAKEIOTTE(pa,w,c,s) (((pa)&IOTTE_PAMASK)|((w)?IOTTE_W:0)|((c)?IOTTE_C:0)|((s)?IOTTE_STREAM:0)|(IOTTE_V|IOTTE_8K))
! 136: #define IOTSBSLOT(va,sz) ((u_int)(((vaddr_t)(va))-(is->is_dvmabase))>>PGSHIFT)
! 137:
! 138: /*
! 139: * interrupt map stuff. this belongs elsewhere.
! 140: */
! 141:
! 142: #define INTMAP_V 0x080000000LL /* Interrupt valid (enabled) */
! 143: #define INTMAP_TID 0x07c000000LL /* UPA target ID mask */
! 144: #define INTMAP_IGN 0x0000007c0LL /* Interrupt group no (sbus only). */
! 145: #define INTMAP_IGN_SHIFT 6
! 146: #define INTMAP_INO 0x00000003fLL /* Interrupt number */
! 147: #define INTMAP_INR (INTMAP_IGN|INTMAP_INO)
! 148: #define INTMAP_SBUSSLOT 0x000000018LL /* SBus slot # */
! 149: #define INTMAP_PCIBUS 0x000000010LL /* PCI bus number (A or B) */
! 150: #define INTMAP_PCISLOT 0x00000000cLL /* PCI slot # */
! 151: #define INTMAP_PCIINT 0x000000003LL /* PCI interrupt #A,#B,#C,#D */
! 152: #define INTMAP_OBIO 0x000000020LL /* Onboard device */
! 153: #define INTMAP_LSHIFT 11 /* Encode level in vector */
! 154: #define INTLEVENCODE(x) (((x)&0x0f)<<INTMAP_LSHIFT)
! 155: #define INTLEV(x) (((x)>>INTMAP_LSHIFT)&0x0f)
! 156: #define INTVEC(x) ((x)&INTMAP_INR)
! 157: #define INTSLOT(x) (((x)>>3)&0x7)
! 158: #define INTPRI(x) ((x)&0x7)
! 159: #define INTIGN(x) ((x)&INTMAP_IGN)
! 160: #define INTINO(x) ((x)&INTMAP_INO)
! 161: #define INTTID_SHIFT 26
! 162: #define INTTID(x) (((x) & INTMAP_TID) >> INTTID_SHIFT)
! 163:
! 164: #define INTPCI_MAXOBINO 0x16 /* maximum OBIO INO value for PCI */
! 165: #define INTPCIOBINOX(x) ((x)&0x1f) /* OBIO ino index (for PCI machines) */
! 166: #define INTPCIINOX(x) (((x)&0x1c)>>2) /* PCI ino index */
! 167:
! 168: #define INTCLR_IDLE 0
! 169:
! 170: #endif /* _SPARC64_DEV_IOMMUREG_H_ */
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