Annotation of sys/arch/sparc64/dev/ebusreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ebusreg.h,v 1.5 2007/04/04 18:38:54 kettenis Exp $ */
2: /* $NetBSD: ebusreg.h,v 1.1 1999/06/04 13:29:13 mrg Exp $ */
3:
4: /*
5: * Copyright (c) 1999 Matthew R. Green
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. The name of the author may not be used to endorse or promote products
17: * derived from this software without specific prior written permission.
18: *
19: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24: * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25: * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26: * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27: * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29: * SUCH DAMAGE.
30: */
31:
32: #ifndef _SPARC64_DEV_EBUSREG_H_
33: #define _SPARC64_DEV_EBUSREG_H_
34:
35: /*
36: * UltraSPARC `ebus'
37: *
38: * The `ebus' bus is designed to plug traditional PC-ISA devices into
39: * an SPARC system with as few costs as possible, without sacrificing
40: * to performance. Typically, it is implemented in the PCIO IC from
41: * SME, which also implements a `hme-compatible' PCI network device
42: * (`network'). The ebus has 4 DMA channels, similar to the DMA seen
43: * in the ESP SCSI DMA.
44: *
45: * Typical UltraSPARC systems have a NatSemi SuperIO IC to provide
46: * serial ports for the keyboard and mouse (`se'), floppy disk
47: * controller (`fdthree'), parallel port controller (`bpp') connected
48: * to the ebus, and a PCI-IDE controller (connected directly to the
49: * PCI bus, of course), as well as a Siemens Nixdorf SAB82532 dual
50: * channel serial controller (`su' providing ttya and ttyb), an MK48T59
51: * EEPROM/clock controller (also where the idprom, including the
52: * ethernet address, is located), the audio system (`SUNW,CS4231', same
53: * as other UltraSPARC and some SPARC systems), and other various
54: * internal devices found on traditional SPARC systems such as the
55: * `power', `flashprom', etc., devices.
56: *
57: * The ebus uses an interrupt mapping scheme similar to PCI, though
58: * the actual structures are different.
59: */
60:
61: /*
62: * ebus PROM structures
63: */
64:
65: struct ebus_regs {
66: u_int32_t hi; /* high bits of physaddr */
67: u_int32_t lo;
68: u_int32_t size;
69: };
70:
71: #define EBUS_PADDR_FROM_REG(reg) ((((paddr_t)((reg)->hi)) << 32UL) | ((paddr_t)(reg)->lo))
72:
73: struct ebus_ranges {
74: u_int32_t child_hi; /* child high phys addr */
75: u_int32_t child_lo; /* child low phys addr */
76: u_int32_t phys_hi; /* parent high phys addr */
77: u_int32_t phys_mid; /* parent mid phys addr */
78: u_int32_t phys_lo; /* parent low phys addr */
79: u_int32_t size;
80: };
81:
82: struct ebus_mainbus_ranges {
83: u_int32_t child_hi;
84: u_int32_t child_lo;
85: u_int32_t phys_hi;
86: u_int32_t phys_lo;
87: u_int32_t size;
88: };
89:
90: struct ebus_interrupt_map {
91: u_int32_t hi; /* high phys addr mask */
92: u_int32_t lo; /* low phys addr mask */
93: u_int32_t intr; /* interrupt mask */
94: int32_t cnode; /* child node */
95: u_int32_t cintr; /* child interrupt */
96: };
97:
98: struct ebus_interrupt_map_mask {
99: u_int32_t hi; /* high phys addr */
100: u_int32_t lo; /* low phys addr */
101: u_int32_t intr; /* interrupt */
102: };
103:
104: /* EBUS dma registers */
105: #define EBDMA_DCSR 0x0 /* control/status */
106: #define EBDMA_DADDR 0x4 /* DMA address */
107: #define EBDMA_DCNT 0x8 /* DMA count */
108:
109: /* EBUS DMA control/status (EBDMA_DCSR) */
110: #define EBDCSR_INT 0x00000001 /* interrupt pending */
111: #define EBDCSR_ERR 0x00000002 /* error pending */
112: #define EBDCSR_DRAIN 0x00000004 /* drain */
113: #define EBDCSR_INTEN 0x00000010 /* interrupt enable */
114: #define EBDCSR_RESET 0x00000080 /* reset */
115: #define EBDCSR_WRITE 0x00000100 /* write */
116: #define EBDCSR_DMAEN 0x00000200 /* dma enable */
117: #define EBDCSR_CYC 0x00000400 /* cyc pending */
118: #define EBDCSR_DIAGRD 0x00000800 /* diagnostic read done */
119: #define EBDCSR_DIAGWR 0x00001000 /* diagnostic write done */
120: #define EBDCSR_CNTEN 0x00002000 /* count enable */
121: #define EBDCSR_TC 0x00004000 /* terminal count */
122: #define EBDCSR_CSRDRNDIS 0x00010000 /* disable csr drain */
123: #define EBDCSR_BURSTMASK 0x000c0000 /* burst size mask */
124: #define EBDCSR_BURST_1 0x00080000 /* burst 1 */
125: #define EBDCSR_BURST_4 0x00000000 /* burst 4 */
126: #define EBDCSR_BURST_8 0x00040000 /* burst 8 */
127: #define EBDCSR_BURST_16 0x000c0000 /* burst 16 */
128: #define EBDCSR_DIAGEN 0x00100000 /* enable diagnostics */
129: #define EBDCSR_ERRDIS 0x00400000 /* disable error pending */
130: #define EBDCSR_TCIDIS 0x00800000 /* disable TCI */
131: #define EBDCSR_NEXTEN 0x01000000 /* enable next */
132: #define EBDCSR_DMAON 0x02000000 /* dma on */
133: #define EBDCSR_A_LOADED 0x04000000 /* address loaded */
134: #define EBDCSR_NA_LOADED 0x08000000 /* next address loaded */
135: #define EBDCSR_DEVMASK 0xf0000000 /* device id mask */
136:
137: #endif /* _SPARC64_DEV_EBUSREG_H_ */
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