Annotation of sys/arch/sparc/sparc/intreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: intreg.h,v 1.8 2006/05/29 20:40:01 miod Exp $ */
2: /* $NetBSD: intreg.h,v 1.6 1997/07/22 20:19:10 pk Exp $ */
3:
4: /*
5: * Copyright (c) 1992, 1993
6: * The Regents of the University of California. All rights reserved.
7: *
8: * This software was developed by the Computer Systems Engineering group
9: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10: * contributed to Berkeley.
11: *
12: * All advertising materials mentioning features or use of this software
13: * must display the following acknowledgement:
14: * This product includes software developed by the University of
15: * California, Lawrence Berkeley Laboratory.
16: *
17: * Redistribution and use in source and binary forms, with or without
18: * modification, are permitted provided that the following conditions
19: * are met:
20: * 1. Redistributions of source code must retain the above copyright
21: * notice, this list of conditions and the following disclaimer.
22: * 2. Redistributions in binary form must reproduce the above copyright
23: * notice, this list of conditions and the following disclaimer in the
24: * documentation and/or other materials provided with the distribution.
25: * 3. Neither the name of the University nor the names of its contributors
26: * may be used to endorse or promote products derived from this software
27: * without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39: * SUCH DAMAGE.
40: *
41: * @(#)intreg.h 8.1 (Berkeley) 6/11/93
42: */
43:
44: #include <sparc/sparc/vaddrs.h>
45:
46: /*
47: * sun4c interrupt enable register.
48: *
49: * The register is a single byte. C code must use the ienab_bis and
50: * ienab_bic functions found in locore.s.
51: *
52: * The register's physical address is defined here as the register
53: * must be mapped early in the boot process (otherwise NMI handling
54: * will fail).
55: */
56: #define INT_ENABLE_REG_PHYSADR 0xf5000000 /* phys addr in IOspace */
57:
58: /*
59: * Bits in interrupt enable register. Software interrupt requests must
60: * be cleared in software. This is done in locore.s. The ALLIE bit must
61: * be cleared to clear asynchronous memory error (level 15) interrupts.
62: */
63: #ifdef solbourne
64: #define IE_L14 14
65: #define IE_L10 10
66: #define IE_L8 8
67: #define IE_L6 6
68: #define IE_L4 4
69: #define IE_L1 1
70: #else
71: #define IE_L14 0x80 /* enable level 14 (counter 1) interrupts */
72: #define IE_L10 0x20 /* enable level 10 (counter 0) interrupts */
73: #define IE_L8 0x10 /* enable level 8 interrupts */
74: #define IE_L6 0x08 /* request software level 6 interrupt */
75: #define IE_L4 0x04 /* request software level 4 interrupt */
76: #define IE_L1 0x02 /* request software level 1 interrupt */
77: #define IE_ALLIE 0x01 /* enable interrupts */
78: #endif
79:
80: #ifndef _LOCORE
81: void ienab_bis(int bis); /* set given bits */
82: void ienab_bic(int bic); /* clear given bits */
83: #endif
84:
85: #if defined(SUN4M)
86: #ifdef notyet
87: #define IENAB_SYS ((_MAXNBPG * _MAXNCPU) + 0xc)
88: #define IENAB_P0 0x0008
89: #define IENAB_P1 0x1008
90: #define IENAB_P2 0x2008
91: #define IENAB_P3 0x3008
92: #endif /* notyet */
93: #endif
94:
95: #if defined(SUN4M)
96: /*
97: * Interrupt Control Registers, located in IO space.
98: * (mapped to `locore' for now..)
99: * There are two sets of interrupt registers called `Processor Interrupts'
100: * and `System Interrupts'. The `Processor' set corresponds to the 15
101: * interrupt levels as seen by the CPU. The `System' set corresponds to
102: * a set of devices supported by the implementing chip-set.
103: *
104: * Briefly, the ICR_PI_* are per-processor interrupts; the ICR_SI_* are
105: * system-wide interrupts, and the ICR_ITR selects the processor to get
106: * the system's interrupts.
107: */
108: #define ICR_PI_PEND (PI_INTR_VA + 0x0)
109: #define ICR_PI_CLR (PI_INTR_VA + 0x4)
110: #define ICR_PI_SET (PI_INTR_VA + 0x8)
111: #define ICR_SI_PEND (SI_INTR_VA)
112: #define ICR_SI_MASK (SI_INTR_VA + 0x4)
113: #define ICR_SI_CLR (SI_INTR_VA + 0x8)
114: #define ICR_SI_SET (SI_INTR_VA + 0xc)
115: #define ICR_ITR (SI_INTR_VA + 0x10)
116:
117: /*
118: * Bits in interrupt registers. Software interrupt requests must
119: * be cleared in software. This is done in locore.s.
120: * There are separate registers for reading pending interrupts and
121: * setting/clearing (software) interrupts.
122: */
123: #define PINTR_SINTRLEV(n) (1 << (16 + (n)))
124: #define PINTR_IC 0x8000 /* Level 15 clear */
125:
126: #define SINTR_MA 0x80000000 /* Mask All interrupts */
127: #define SINTR_ME 0x40000000 /* Module Error (async) */
128: #define SINTR_I 0x20000000 /* MSI (MBus-SBus) */
129: #define SINTR_M 0x10000000 /* ECC Memory controller */
130: #define SINTR_V 0x08000000 /* VME Async error */
131: #define SINTR_RSVD2 0x07800000
132: #define SINTR_F 0x00400000 /* Floppy */
133: #define SINTR_MI 0x00200000 /* Module interrupt */
134: #define SINTR_VI 0x00100000 /* Video (Supersparc only) */
135: #define SINTR_T 0x00080000 /* Level 10 counter */
136: #define SINTR_SC 0x00040000 /* SCSI */
137: #define SINTR_A 0x00020000 /* Audio/ISDN */
138: #define SINTR_E 0x00010000 /* Ethernet */
139: #define SINTR_S 0x00008000 /* Serial port */
140: #define SINTR_K 0x00004000 /* Keyboard/mouse */
141: #define SINTR_SBUSMASK 0x00003f80 /* SBus */
142: #define SINTR_SBUS(n) (1 << (7+(n)-1))
143: #define SINTR_VMEMASK 0x0000007f /* VME */
144: #define SINTR_VME(n) (1 << ((n)-1))
145: #define SINTR_BITS "\020" \
146: "\01VME0\02VME1\03VME2\04VME3\05VME4\06VME5" \
147: "\07VME6\010SBUS0\011SBUS1\012SBUS2\013SBUS3" \
148: "\014SBUS4\015SBUS5\016SBUS6\017K\020S\021E" \
149: "\022A\023SC\024T\025VI\065MI\027F" \
150: "\034V\035M\036I\037ME\040MA"
151:
152:
153: #endif
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