Annotation of sys/arch/sparc/sparc/cpuvar.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: cpuvar.h,v 1.11 2007/05/31 19:53:14 sobrado Exp $ */
! 2: /* $NetBSD: cpuvar.h,v 1.4 1997/07/06 21:14:25 pk Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1996 The NetBSD Foundation, Inc.
! 6: * All rights reserved.
! 7: *
! 8: * This code is derived from software contributed to The NetBSD Foundation
! 9: * by Paul Kranenburg.
! 10: *
! 11: * Redistribution and use in source and binary forms, with or without
! 12: * modification, are permitted provided that the following conditions
! 13: * are met:
! 14: * 1. Redistributions of source code must retain the above copyright
! 15: * notice, this list of conditions and the following disclaimer.
! 16: * 2. Redistributions in binary form must reproduce the above copyright
! 17: * notice, this list of conditions and the following disclaimer in the
! 18: * documentation and/or other materials provided with the distribution.
! 19: * 3. All advertising materials mentioning features or use of this software
! 20: * must display the following acknowledgement:
! 21: * This product includes software developed by the NetBSD
! 22: * Foundation, Inc. and its contributors.
! 23: * 4. Neither the name of The NetBSD Foundation nor the names of its
! 24: * contributors may be used to endorse or promote products derived
! 25: * from this software without specific prior written permission.
! 26: *
! 27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
! 28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE
! 31: * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 37: * POSSIBILITY OF SUCH DAMAGE.
! 38: */
! 39:
! 40: #ifndef _SPARC_CPUVAR_H
! 41: #define _SPARC_CPUVAR_H
! 42:
! 43: #include <sys/device.h>
! 44: #include <sys/sched.h>
! 45:
! 46: #include <sparc/sparc/cache.h> /* for cacheinfo */
! 47:
! 48: /*
! 49: * CPU/MMU module information.
! 50: * There is one of these for each "mainline" CPU module we support.
! 51: * The information contained in the structure is used only during
! 52: * auto-configuration of the CPUs; some fields are copied into the
! 53: * per-cpu data structure (cpu_softc) for easy access during normal
! 54: * operation.
! 55: */
! 56: struct cpu_softc;
! 57: struct module_info {
! 58: int cpu_type;
! 59: enum vactype vactype;
! 60: void (*cpu_match)(struct cpu_softc *, struct module_info *, int);
! 61: void (*getcacheinfo)(struct cpu_softc *sc, int node);
! 62: void (*hotfix)(struct cpu_softc *);
! 63: void (*mmu_enable)(void);
! 64: void (*cache_enable)(void);
! 65: int ncontext; /* max. # of contexts (we use) */
! 66:
! 67: void (*get_syncflt)(void);
! 68: int (*get_asyncflt)(u_int *, u_int *);
! 69: void (*cache_flush)(caddr_t, u_int);
! 70: void (*vcache_flush_page)(int);
! 71: void (*vcache_flush_segment)(int, int);
! 72: void (*vcache_flush_region)(int);
! 73: void (*vcache_flush_context)(void);
! 74: void (*pcache_flush_line)(int, int);
! 75: void (*pure_vcache_flush)(void);
! 76: void (*cache_flush_all)(void);
! 77: void (*memerr)(unsigned, u_int, u_int, struct trapframe *);
! 78: };
! 79:
! 80:
! 81: struct cpu_softc;
! 82: struct cpu_info {
! 83: struct cpu_softc *ci_softc;
! 84:
! 85: struct proc *ci_curproc;
! 86: struct cpu_info *ci_next;
! 87:
! 88: struct schedstate_percpu ci_schedstate;
! 89: };
! 90:
! 91: #define curcpu() (&cpuinfo.ci)
! 92: #define cpu_number() (cpuinfo.mid)
! 93: #define CPU_IS_PRIMARY(ci) ((ci)->ci_softc->master)
! 94: #define CPU_INFO_ITERATOR int
! 95: #define CPU_INFO_FOREACH(cii, ci) \
! 96: for (cii = 0, ci = curcpu(); ci != NULL; ci = ci->ci_next)
! 97:
! 98: /*
! 99: * The cpu_softc structure. This structure maintains information about one
! 100: * currently installed CPU (there may be several of these if the machine
! 101: * supports multiple CPUs, as on some Sun4m architectures). The information
! 102: * in this structure supersedes the old "cpumod", "mmumod", and similar
! 103: * fields.
! 104: */
! 105:
! 106: struct cpu_softc {
! 107: struct device dv; /* generic device info */
! 108:
! 109: struct cpu_info ci;
! 110:
! 111: int node; /* PROM node for this CPU */
! 112:
! 113: /* CPU information */
! 114: char *cpu_name; /* CPU model */
! 115: int cpu_impl; /* CPU implementation code */
! 116: int cpu_vers; /* CPU version code */
! 117: int mmu_impl; /* MMU implementation code */
! 118: int mmu_vers; /* MMU version code */
! 119: int master; /* 1 if this is bootup CPU */
! 120:
! 121: int mid; /* Module ID for MP systems */
! 122: int mbus; /* 1 if CPU is on MBus */
! 123: int mxcc; /* 1 if a MBus-level MXCC is present */
! 124:
! 125: caddr_t mailbox; /* VA of CPU's mailbox */
! 126:
! 127:
! 128: int mmu_ncontext; /* Number of contexts supported */
! 129: int mmu_nregion; /* Number of regions supported */
! 130: int mmu_nsegment; /* [4/4c] Segments */
! 131: int mmu_npmeg; /* [4/4c] Pmegs */
! 132: int sun4_mmu3l; /* [4]: 3-level MMU present */
! 133: #if defined(SUN4_MMU3L)
! 134: #define HASSUN4_MMU3L (cpuinfo.sun4_mmu3l)
! 135: #else
! 136: #define HASSUN4_MMU3L (0)
! 137: #endif
! 138:
! 139: /* Context administration */
! 140: int *ctx_tbl; /* [4m] SRMMU-edible context table */
! 141: union ctxinfo *ctxinfo;
! 142: union ctxinfo *ctx_freelist; /* context free list */
! 143: int ctx_kick; /* allocation rover when none free */
! 144: int ctx_kickdir; /* ctx_kick roves both directions */
! 145:
! 146: /* MMU tables that map `cpuinfo'' on each CPU */
! 147: int *L1_ptps; /* XXX */
! 148:
! 149: /* XXX - of these, we currently use only cpu_type */
! 150: int arch; /* Architecture: CPU_SUN4x */
! 151: int class; /* Class: SuperSPARC, microSPARC... */
! 152: int classlvl; /* Iteration in class: 1, 2, etc. */
! 153: int classsublvl; /* stepping in class (version) */
! 154: int cpu_type; /* Type: see CPUTYP_xxx below */
! 155:
! 156: int hz; /* Clock speed */
! 157:
! 158: /* Cache information */
! 159: struct cacheinfo cacheinfo; /* see cache.h */
! 160:
! 161: /* FPU information */
! 162: int fpupresent; /* true if FPU is present */
! 163: int fpuvers; /* FPU revision */
! 164:
! 165: /* various flags to workaround anomalies in chips */
! 166: int flags; /* see CPUFLG_xxx, below */
! 167:
! 168: /*
! 169: * The following pointers point to processes that are somehow
! 170: * associated with this CPU--running on it, using its FPU,
! 171: * etc.
! 172: *
! 173: * XXXMP: much more needs to go here
! 174: */
! 175: struct proc *fpproc; /* FPU owner */
! 176:
! 177: /*
! 178: * The following are function pointers to do interesting CPU-dependent
! 179: * things without having to do type-tests all the time
! 180: */
! 181:
! 182: /* bootup things: access to physical memory */
! 183: u_int (*read_physmem)(u_int addr, int space);
! 184: void (*write_physmem)(u_int addr, u_int data);
! 185: void (*cache_tablewalks)(void);
! 186: void (*mmu_enable)(void);
! 187: void (*hotfix)(struct cpu_softc *);
! 188:
! 189: /* locore defined: */
! 190: void (*get_syncflt)(void); /* Not C-callable */
! 191: int (*get_asyncflt)(u_int *, u_int *);
! 192:
! 193: /* Synchronous Fault Status; temporary storage */
! 194: struct {
! 195: int sfsr;
! 196: int sfva;
! 197: } syncfltdump;
! 198:
! 199: /* Cache handling functions */
! 200: void (*cache_enable)(void);
! 201: void (*cache_flush)(caddr_t, u_int);
! 202: void (*vcache_flush_page)(int);
! 203: void (*vcache_flush_segment)(int, int);
! 204: void (*vcache_flush_region)(int);
! 205: void (*vcache_flush_context)(void);
! 206: void (*pcache_flush_line)(int, int);
! 207: void (*pure_vcache_flush)(void);
! 208: void (*cache_flush_all)(void);
! 209:
! 210: #ifdef SUN4M
! 211: /* hardware-assisted block operation routines */
! 212: void (*hwbcopy)(const void *from, void *to, size_t len);
! 213: void (*hwbzero)(void *buf, size_t len);
! 214:
! 215: /* routine to clear mbus-sbus buffers */
! 216: void (*mbusflush)(void);
! 217: #endif
! 218:
! 219: /*
! 220: * Memory error handler; parity errors, unhandled NMIs and other
! 221: * unrecoverable faults end up here.
! 222: */
! 223: void (*memerr)(unsigned, u_int, u_int, struct trapframe *);
! 224: /* XXX: Add more here! */
! 225: };
! 226:
! 227: /*
! 228: * CPU architectures
! 229: */
! 230: #define CPUARCH_UNKNOWN 0
! 231: #define CPUARCH_SUN4 1
! 232: #define CPUARCH_SUN4C 2
! 233: #define CPUARCH_SUN4M 3
! 234: #define CPUARCH_SUN4D 4
! 235: #define CPUARCH_SUN4U 5
! 236:
! 237: /*
! 238: * CPU classes
! 239: */
! 240: #define CPUCLS_UNKNOWN 0
! 241:
! 242: #if defined(SUN4)
! 243: #define CPUCLS_SUN4 1
! 244: #endif
! 245:
! 246: #if defined(SUN4C)
! 247: #define CPUCLS_SUN4C 5
! 248: #endif
! 249:
! 250: #if defined(SUN4M)
! 251: #define CPUCLS_MICROSPARC 10 /* MicroSPARC-II */
! 252: #define CPUCLS_SUPERSPARC 11 /* Generic SuperSPARC */
! 253: #define CPUCLS_HYPERSPARC 12 /* Ross HyperSPARC RT620 */
! 254: #endif
! 255:
! 256: /*
! 257: * CPU types. Each of these should uniquely identify one platform/type of
! 258: * system, i.e. "MBus-based 75 MHz SuperSPARC-II with ECache" is
! 259: * CPUTYP_SS2_MBUS_MXCC. The general form is
! 260: * CPUTYP_proctype_bustype_cachetype_etc_etc
! 261: *
! 262: * XXX: This is far from complete/comprehensive
! 263: * XXX: ADD SUN4, SUN4C TYPES
! 264: */
! 265: #define CPUTYP_UNKNOWN 0
! 266:
! 267: #define CPUTYP_4_100 1 /* Sun4/100 */
! 268: #define CPUTYP_4_200 2 /* Sun4/200 */
! 269: #define CPUTYP_4_300 3 /* Sun4/300 */
! 270: #define CPUTYP_4_400 4 /* Sun4/400 */
! 271:
! 272: #define CPUTYP_SLC 10 /* SPARCstation SLC */
! 273: #define CPUTYP_ELC 11 /* SPARCstation ELC */
! 274: #define CPUTYP_IPX 12 /* SPARCstation IPX */
! 275: #define CPUTYP_IPC 13 /* SPARCstation IPC */
! 276: #define CPUTYP_1 14 /* SPARCstation 1 */
! 277: #define CPUTYP_1P 15 /* SPARCstation 1+ */
! 278: #define CPUTYP_2 16 /* SPARCstation 2 */
! 279:
! 280: /* We classify the Sun4m's by feature, not by model (XXX: do same for 4/4c) */
! 281: #define CPUTYP_SS2_MBUS_MXCC 20 /* SuperSPARC-II, MBus, MXCC (SS20) */
! 282: #define CPUTYP_SS1_MBUS_MXCC 21 /* SuperSPARC-I, MBus, MXCC (SS10) */
! 283: #define CPUTYP_SS2_MBUS_NOMXCC 22 /* SuperSPARC-II, on MBus w/o MXCC */
! 284: #define CPUTYP_SS1_MBUS_NOMXCC 23 /* SuperSPARC-I, on MBus w/o MXCC */
! 285: #define CPUTYP_MS2 24 /* MicroSPARC-2 */
! 286: #define CPUTYP_MS1 25 /* MicroSPARC-1 */
! 287: #define CPUTYP_HS_MBUS 26 /* MBus-based HyperSPARC */
! 288: #define CPUTYP_CYPRESS 27 /* MBus-based Cypress */
! 289:
! 290: /*
! 291: * CPU flags
! 292: */
! 293: #define CPUFLG_CACHEPAGETABLES 0x1 /* caching pagetables OK on Sun4m */
! 294: #define CPUFLG_CACHEIOMMUTABLES 0x2 /* caching IOMMU translations OK */
! 295: #define CPUFLG_CACHEDVMA 0x4 /* DVMA goes through cache */
! 296: #define CPUFLG_SUN4CACHEBUG 0x8 /* trap page can't be cached */
! 297: #define CPUFLG_CACHE_MANDATORY 0x10 /* if cache is on, don't use
! 298: uncached access */
! 299:
! 300: /*
! 301: * Related function prototypes
! 302: */
! 303: void getcpuinfo(struct cpu_softc *sc, int node);
! 304: void mmu_install_tables(struct cpu_softc *);
! 305: void pmap_alloc_cpu(struct cpu_softc *);
! 306:
! 307: #define cpuinfo (*(struct cpu_softc *)CPUINFO_VA)
! 308: #endif /* _SPARC_CPUVAR_H */
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