Annotation of sys/arch/sparc/sparc/cache.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cache.h,v 1.10 2007/01/22 19:39:33 miod Exp $ */
2: /* $NetBSD: cache.h,v 1.16 1997/07/06 21:15:14 pk Exp $ */
3:
4: /*
5: * Copyright (c) 1996
6: * The President and Fellows of Harvard College. All rights reserved.
7: * Copyright (c) 1992, 1993
8: * The Regents of the University of California. All rights reserved.
9: *
10: * This software was developed by the Computer Systems Engineering group
11: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
12: * contributed to Berkeley.
13: *
14: * Redistribution and use in source and binary forms, with or without
15: * modification, are permitted provided that the following conditions
16: * are met:
17: * 1. Redistributions of source code must retain the above copyright
18: * notice, this list of conditions and the following disclaimer.
19: * 2. Redistributions in binary form must reproduce the above copyright
20: * notice, this list of conditions and the following disclaimer in the
21: * documentation and/or other materials provided with the distribution.
22: * 3. All advertising materials mentioning features or use of this software
23: * must display the following acknowledgement:
24: * This product includes software developed by Aaron Brown and
25: * Harvard University.
26: * This product includes software developed by the University of
27: * California, Berkeley and its contributors.
28: * 4. Neither the name of the University nor the names of its contributors
29: * may be used to endorse or promote products derived from this software
30: * without specific prior written permission.
31: *
32: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
33: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
36: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
40: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
42: * SUCH DAMAGE.
43: *
44: * @(#)cache.h 8.1 (Berkeley) 6/11/93
45: */
46:
47: #ifndef SPARC_CACHE_H
48: #define SPARC_CACHE_H
49:
50: /*
51: * Sun-4 and Sun-4c virtual address cache.
52: *
53: * Sun-4 virtual caches come in two flavors, write-through (Sun-4c)
54: * and write-back (Sun-4). The write-back caches are much faster
55: * but require a bit more care.
56: *
57: */
58: enum vactype { VAC_UNKNOWN, VAC_NONE, VAC_WRITETHROUGH, VAC_WRITEBACK };
59:
60: /*
61: * Cache tags can be written in control space, and must be set to 0
62: * (or invalid anyway) before turning on the cache. The tags are
63: * addressed as an array of 32-bit structures of the form:
64: *
65: * struct cache_tag {
66: * u_int :7, (unused; must be zero)
67: * ct_cid:3, (context ID)
68: * ct_w:1, (write flag from PTE)
69: * ct_s:1, (supervisor flag from PTE)
70: * ct_v:1, (set => cache entry is valid)
71: * :3, (unused; must be zero)
72: * ct_tid:14, (cache tag ID)
73: * :2; (unused; must be zero)
74: * };
75: *
76: * The SPARCstation 1 cache sees virtual addresses as:
77: *
78: * struct cache_va {
79: * u_int :2, (unused; probably copies of va_tid<13>)
80: * cva_tid:14, (tag ID)
81: * cva_line:12, (cache line number)
82: * cva_byte:4; (byte in cache line)
83: * };
84: *
85: * (The SS2 cache is similar but has half as many lines, each twice as long.)
86: *
87: * Note that, because the 12-bit line ID is `wider' than the page offset,
88: * it is possible to have one page map to two different cache lines.
89: * This can happen whenever two different physical pages have the same bits
90: * in the part of the virtual address that overlaps the cache line ID, i.e.,
91: * bits <15:12>. In order to prevent cache duplication, we have to
92: * make sure that no one page has more than one virtual address where
93: * (va1 & 0xf000) != (va2 & 0xf000). (The cache hardware turns off ct_v
94: * when a cache miss occurs on a write, i.e., if va1 is in the cache and
95: * va2 is not, and you write to va2, va1 goes out of the cache. If va1
96: * is in the cache and va2 is not, reading va2 also causes va1 to become
97: * uncached, and the [same] data is then read from main memory into the
98: * cache.)
99: *
100: * The other alternative, of course, is to disable caching of aliased
101: * pages. (In a few cases this might be faster anyway, but we do it
102: * only when forced.)
103: *
104: * The Sun4, since it has an 8K pagesize instead of 4K, needs to check
105: * bits that are one position higher.
106: */
107:
108: /* Some more well-known values: */
109:
110: #define CACHE_ALIAS_DIST_SUN4 0x20000
111: #define CACHE_ALIAS_DIST_SUN4C 0x10000
112:
113: #define CACHE_ALIAS_BITS_SUN4 0x1e000
114: #define CACHE_ALIAS_BITS_SUN4C 0xf000
115:
116: #define CACHE_ALIAS_DIST_HS128k 0x20000
117: #define CACHE_ALIAS_BITS_HS128k 0x1f000
118: #define CACHE_ALIAS_DIST_HS256k 0x40000
119: #define CACHE_ALIAS_BITS_HS256k 0x3f000
120:
121: extern int cache_alias_dist;
122: extern int cache_alias_bits;
123:
124: /* Optimize cache alias macros on single architecture kernels */
125: #if defined(SUN4) && !defined(SUN4C) && !defined(SUN4M)
126: #define CACHE_ALIAS_DIST CACHE_ALIAS_DIST_SUN4
127: #define CACHE_ALIAS_BITS CACHE_ALIAS_BITS_SUN4
128: #elif !defined(SUN4) && defined(SUN4C) && !defined(SUN4M)
129: #define CACHE_ALIAS_DIST CACHE_ALIAS_DIST_SUN4C
130: #define CACHE_ALIAS_BITS CACHE_ALIAS_BITS_SUN4C
131: #else
132: #define CACHE_ALIAS_DIST cache_alias_dist
133: #define CACHE_ALIAS_BITS cache_alias_bits
134: #endif
135:
136: /*
137: * True iff a1 and a2 are `bad' aliases (will cause cache duplication).
138: */
139: #define BADALIAS(a1, a2) (((int)(a1) ^ (int)(a2)) & CACHE_ALIAS_BITS)
140:
141: /*
142: * Routines for dealing with the cache.
143: */
144: void sun4_cache_enable(void); /* turn it on */
145: void ms1_cache_enable(void); /* turn it on */
146: void viking_cache_enable(void); /* turn it on */
147: void hypersparc_cache_enable(void); /* turn it on */
148: void swift_cache_enable(void); /* turn it on */
149: void cypress_cache_enable(void); /* turn it on */
150: void turbosparc_cache_enable(void); /* turn it on */
151: void kap_cache_enable(void); /* turn it on */
152:
153: void sun4_vcache_flush_context(void); /* flush current context */
154: void sun4_vcache_flush_region(int); /* flush region in cur ctx */
155: void sun4_vcache_flush_segment(int, int); /* flush seg in cur ctx */
156: void sun4_vcache_flush_page(int va); /* flush page in cur ctx */
157: void sun4_cache_flush(caddr_t, u_int); /* flush region */
158:
159: void srmmu_vcache_flush_context(void); /* flush current context */
160: void srmmu_vcache_flush_region(int); /* flush region in cur ctx */
161: void srmmu_vcache_flush_segment(int, int); /* flush seg in cur ctx */
162: void srmmu_vcache_flush_page(int va); /* flush page in cur ctx */
163: void srmmu_cache_flush(caddr_t, u_int); /* flush region */
164: void hypersparc_pure_vcache_flush(void);
165:
166: void ms1_cache_flush_all(void);
167: void srmmu_cache_flush_all(void);
168: void cypress_cache_flush_all(void);
169: void hypersparc_cache_flush_all(void);
170:
171: void ms1_cache_flush(caddr_t, u_int);
172: void viking_cache_flush(caddr_t, u_int);
173: void viking_pcache_flush_line(int, int);
174: void srmmu_pcache_flush_line(int, int);
175:
176: void kap_vcache_flush_context(void); /* flush current context */
177: void kap_vcache_flush_page(int va); /* flush page in cur ctx */
178: void kap_cache_flush(caddr_t, u_int); /* flush region */
179:
180: extern void sparc_noop(void);
181:
182: #define noop_vcache_flush_context \
183: (void (*)(void)) sparc_noop
184: #define noop_vcache_flush_region \
185: (void (*)(int)) sparc_noop
186: #define noop_vcache_flush_segment \
187: (void (*)(int,int)) sparc_noop
188: #define noop_vcache_flush_page \
189: (void (*)(int)) sparc_noop
190: #define noop_cache_flush \
191: (void (*)(caddr_t, u_int)) sparc_noop
192: #define noop_pcache_flush_line \
193: (void (*)(int, int)) sparc_noop
194: #define noop_pure_vcache_flush \
195: (void (*)(void)) sparc_noop
196: #define noop_cache_flush_all \
197: (void (*)(void)) sparc_noop
198:
199: #define cache_flush_page(va) cpuinfo.vcache_flush_page(va)
200: #define cache_flush_segment(vr,vs) cpuinfo.vcache_flush_segment(vr,vs)
201: #define cache_flush_region(vr) cpuinfo.vcache_flush_region(vr)
202: #define cache_flush_context() cpuinfo.vcache_flush_context()
203:
204: /*
205: * Cache control information.
206: */
207: struct cacheinfo {
208: int c_totalsize; /* total size, in bytes */
209: /* if split, MAX(icache,dcache) */
210: int c_enabled; /* true => cache is enabled */
211: int c_hwflush; /* true => have hardware flush */
212: int c_linesize; /* line size, in bytes */
213: int c_l2linesize; /* log2(linesize) */
214: int c_nlines; /* number of cache lines */
215: int c_physical; /* true => cache has physical
216: address tags */
217: int c_associativity; /* # of "buckets" in cache line */
218: int c_split; /* true => cache is split */
219:
220: int ic_totalsize; /* instruction cache */
221: int ic_enabled;
222: int ic_linesize;
223: int ic_l2linesize;
224: int ic_nlines;
225: int ic_associativity;
226:
227: int dc_totalsize; /* data cache */
228: int dc_enabled;
229: int dc_linesize;
230: int dc_l2linesize;
231: int dc_nlines;
232: int dc_associativity;
233:
234: int ec_totalsize; /* external cache info */
235: int ec_enabled;
236: int ec_linesize;
237: int ec_l2linesize;
238: int ec_nlines;
239: int ec_associativity;
240:
241: enum vactype c_vactype;
242: };
243:
244: #define CACHEINFO cpuinfo.cacheinfo
245:
246: /*
247: * Cache control statistics.
248: */
249: struct cachestats {
250: int cs_npgflush; /* # page flushes */
251: int cs_nsgflush; /* # seg flushes */
252: int cs_nrgflush; /* # seg flushes */
253: int cs_ncxflush; /* # context flushes */
254: int cs_nraflush; /* # range flushes */
255: #ifdef notyet
256: int cs_ra[65]; /* pages/range */
257: #endif
258: };
259: #endif /* SPARC_CACHE_H */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to cache.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / sparc / sparc