Annotation of sys/arch/sparc/include/psl.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: psl.h,v 1.23 2007/05/16 19:37:06 thib Exp $ */
2: /* $NetBSD: psl.h,v 1.12 1997/03/10 21:49:11 pk Exp $ */
3:
4: /*
5: * Copyright (c) 1992, 1993
6: * The Regents of the University of California. All rights reserved.
7: *
8: * This software was developed by the Computer Systems Engineering group
9: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10: * contributed to Berkeley.
11: *
12: * All advertising materials mentioning features or use of this software
13: * must display the following acknowledgement:
14: * This product includes software developed by the University of
15: * California, Lawrence Berkeley Laboratory.
16: *
17: * Redistribution and use in source and binary forms, with or without
18: * modification, are permitted provided that the following conditions
19: * are met:
20: * 1. Redistributions of source code must retain the above copyright
21: * notice, this list of conditions and the following disclaimer.
22: * 2. Redistributions in binary form must reproduce the above copyright
23: * notice, this list of conditions and the following disclaimer in the
24: * documentation and/or other materials provided with the distribution.
25: * 3. Neither the name of the University nor the names of its contributors
26: * may be used to endorse or promote products derived from this software
27: * without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39: * SUCH DAMAGE.
40: *
41: * @(#)psl.h 8.1 (Berkeley) 6/11/93
42: */
43:
44: #ifndef PSR_IMPL
45:
46: /*
47: * SPARC Process Status Register (in psl.h for hysterical raisins).
48: *
49: * The picture in the Sun manuals looks like this:
50: * 1 1
51: * 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0
52: * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
53: * | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP |
54: * | | |n z v c| |C|F| | |S|T| |
55: * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
56: */
57:
58: #define PSR_IMPL 0xf0000000 /* implementation */
59: #define PSR_VER 0x0f000000 /* version */
60: #define PSR_ICC 0x00f00000 /* integer condition codes */
61: #define PSR_N 0x00800000 /* negative */
62: #define PSR_Z 0x00400000 /* zero */
63: #define PSR_O 0x00200000 /* overflow */
64: #define PSR_C 0x00100000 /* carry */
65: #define PSR_EC 0x00002000 /* coprocessor enable */
66: #define PSR_EF 0x00001000 /* FP enable */
67: #define PSR_PIL 0x00000f00 /* interrupt level */
68: #define PSR_S 0x00000080 /* supervisor (kernel) mode */
69: #define PSR_PS 0x00000040 /* previous supervisor mode (traps) */
70: #define PSR_ET 0x00000020 /* trap enable */
71: #define PSR_CWP 0x0000001f /* current window pointer */
72:
73: #define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET"
74:
75: /*
76: * Various interrupt levels.
77: */
78: #define IPL_NONE 0
79: #define IPL_SOFTINT 1
80: #define IPL_SOFTCLOCK IPL_SOFTINT /* softclock() interrupts */
81: #define IPL_SOFTNET IPL_SOFTINT /* soft network interrupts */
82: #define IPL_AUSOFT 4 /* audio soft interrupts */
83: #define IPL_FDSOFT 4 /* floppy soft interrupts */
84: #define IPL_BIO 5 /* block devices are at 5 and below */
85: #define IPL_TTY 6 /* tty soft interrupts */
86: #define IPL_NET 7 /* network hardware at 7 or below */
87: #define IPL_VM 7 /* max(BIO, NET, TTY) */
88: #define IPL_FB 9 /* framebuffer interrupts */
89: #define IPL_CLOCK 10 /* hardclock() */
90: #define IPL_FD 11 /* hard floppy interrupts. */
91: #define IPL_ZS 12 /* zs interrupts */
92: /*
93: * XXX - this is called AUHARD instead of AUDIO because of some confusion
94: * with how MI audio code handles this. Stay tuned for a change in the future
95: */
96: #define IPL_AUHARD 13 /* hard audio interrupts */
97: #define IPL_STATCLOCK 14 /* statclock() */
98: #define IPL_SCHED IPL_STATCLOCK
99: #define IPL_HIGH 15 /* splhigh() */
100:
101: #if defined(_KERNEL) && !defined(_LOCORE)
102:
103: static __inline int getpsr(void);
104: static __inline void setpsr(int);
105: static __inline int spl0(void);
106: static __inline int splhigh(void);
107: static __inline void splx(int);
108: static __inline int getmid(void);
109:
110: /*
111: * GCC pseudo-functions for manipulating PSR (primarily PIL field).
112: */
113: static __inline int
114: getpsr()
115: {
116: int psr;
117:
118: __asm __volatile("rd %%psr,%0" : "=r" (psr));
119: return (psr);
120: }
121:
122: static __inline int
123: getmid()
124: {
125: int mid;
126:
127: __asm __volatile("rd %%tbr,%0" : "=r" (mid));
128: return ((mid >> 20) & 0x3);
129: }
130:
131: static __inline void
132: setpsr(newpsr)
133: int newpsr;
134: {
135: __asm __volatile("wr %0,0,%%psr" : : "r" (newpsr));
136: __asm __volatile("nop");
137: __asm __volatile("nop");
138: __asm __volatile("nop");
139: }
140:
141: static __inline int
142: spl0()
143: {
144: int psr, oldipl;
145:
146: /*
147: * wrpsr xors two values: we choose old psr and old ipl here,
148: * which gives us the same value as the old psr but with all
149: * the old PIL bits turned off.
150: */
151: __asm __volatile("rd %%psr,%0" : "=r" (psr));
152: oldipl = psr & PSR_PIL;
153: __asm __volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl));
154:
155: /*
156: * Three instructions must execute before we can depend
157: * on the bits to be changed.
158: */
159: __asm __volatile("nop; nop; nop");
160: return (oldipl);
161: }
162:
163: #ifdef DIAGNOSTIC
164: /*
165: * Although this function is implemented in MI code, it must be in this MD
166: * header because we don't want this header to include MI includes.
167: */
168: void splassert_fail(int, int, const char *);
169: extern int splassert_ctl;
170: void splassert_check(int, const char *);
171: #define splassert(__wantipl) do { \
172: if (splassert_ctl > 0) { \
173: splassert_check(__wantipl, __func__); \
174: } \
175: } while (0)
176: #else
177: #define splassert(wantipl) do { /* nada */ } while (0)
178: #endif
179:
180: /*
181: * PIL 1 through 14 can use this macro.
182: * (spl0 and splhigh are special since they put all 0s or all 1s
183: * into the ipl field.)
184: */
185: #define SPL(name, newipl) \
186: static __inline int name(void); \
187: static __inline int name() \
188: { \
189: int psr, oldipl; \
190: __asm __volatile("rd %%psr,%0" : "=r" (psr)); \
191: oldipl = psr & PSR_PIL; \
192: psr &= ~oldipl; \
193: __asm __volatile("wr %0,%1,%%psr" : : \
194: "r" (psr), "n" ((newipl) << 8)); \
195: __asm __volatile("nop; nop; nop"); \
196: __asm __volatile("":::"memory"); /* protect from reordering */ \
197: return (oldipl); \
198: }
199: /* A non-priority-decreasing version of SPL */
200: #define SPLHOLD(name, newipl) \
201: static __inline int name(void); \
202: static __inline int name() \
203: { \
204: int psr, oldipl; \
205: __asm __volatile("rd %%psr,%0" : "=r" (psr)); \
206: oldipl = psr & PSR_PIL; \
207: if ((newipl << 8) <= oldipl) \
208: return oldipl; \
209: psr &= ~oldipl; \
210: __asm __volatile("wr %0,%1,%%psr" : : \
211: "r" (psr), "n" ((newipl) << 8)); \
212: __asm __volatile("nop; nop; nop"); \
213: __asm __volatile("":::"memory"); /* protect from reordering */ \
214: return (oldipl); \
215: }
216:
217: SPLHOLD(splsoftint, IPL_SOFTINT)
218: #define splsoftclock splsoftint
219: #define splsoftnet splsoftint
220: SPLHOLD(splausoft, IPL_AUSOFT)
221: SPLHOLD(splfdsoft, IPL_FDSOFT)
222: SPLHOLD(splbio, IPL_BIO)
223: SPLHOLD(splnet, IPL_NET)
224: SPLHOLD(spltty, IPL_TTY)
225: SPLHOLD(splvm, IPL_VM)
226: SPLHOLD(splclock, IPL_CLOCK)
227: SPLHOLD(splfd, IPL_FD)
228: SPLHOLD(splzs, IPL_ZS)
229: SPLHOLD(splaudio, IPL_AUHARD)
230: SPLHOLD(splsched, IPL_SCHED)
231: SPLHOLD(splstatclock, IPL_STATCLOCK)
232:
233: static __inline int splhigh()
234: {
235: int psr, oldipl;
236:
237: __asm __volatile("rd %%psr,%0" : "=r" (psr));
238: __asm __volatile("wr %0,0,%%psr" : : "r" (psr | PSR_PIL));
239: __asm __volatile("and %1,%2,%0; nop; nop" : "=r" (oldipl) : \
240: "r" (psr), "n" (PSR_PIL));
241: __asm __volatile("":::"memory"); /* protect from reordering */
242: return (oldipl);
243: }
244:
245: /* splx does not have a return value */
246: static __inline void splx(newipl)
247: int newipl;
248: {
249: int psr;
250:
251: __asm __volatile("":::"memory"); /* protect from reordering */
252: __asm __volatile("rd %%psr,%0" : "=r" (psr));
253: __asm __volatile("wr %0,%1,%%psr" : : \
254: "r" (psr & ~PSR_PIL), "rn" (newipl));
255: __asm __volatile("nop; nop; nop");
256: }
257: #endif /* KERNEL && !_LOCORE */
258:
259: #endif /* PSR_IMPL */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to psl.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / sparc / include