Annotation of sys/arch/sparc/include/instr.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: instr.h,v 1.4 2003/07/14 00:45:20 jason Exp $ */
2: /* $NetBSD: instr.h,v 1.3 1997/03/14 23:54:07 christos Exp $ */
3:
4: /*
5: * Copyright (c) 1992, 1993
6: * The Regents of the University of California. All rights reserved.
7: *
8: * This software was developed by the Computer Systems Engineering group
9: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10: * contributed to Berkeley.
11: *
12: * All advertising materials mentioning features or use of this software
13: * must display the following acknowledgement:
14: * This product includes software developed by the University of
15: * California, Lawrence Berkeley Laboratory.
16: *
17: * Redistribution and use in source and binary forms, with or without
18: * modification, are permitted provided that the following conditions
19: * are met:
20: * 1. Redistributions of source code must retain the above copyright
21: * notice, this list of conditions and the following disclaimer.
22: * 2. Redistributions in binary form must reproduce the above copyright
23: * notice, this list of conditions and the following disclaimer in the
24: * documentation and/or other materials provided with the distribution.
25: * 3. Neither the name of the University nor the names of its contributors
26: * may be used to endorse or promote products derived from this software
27: * without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39: * SUCH DAMAGE.
40: *
41: * @(#)instr.h 8.1 (Berkeley) 6/11/93
42: */
43:
44: /* see also Appendix F of the SPARC version 8 document */
45: enum IOP { IOP_OP2, IOP_CALL, IOP_reg, IOP_mem };
46: enum IOP2 { IOP2_UNIMP, IOP2_err1, IOP2_Bicc, IOP2_err3,
47: IOP2_SETHI, IOP2_err5, IOP2_FBfcc, IOP2_CBccc };
48: enum IOP3_reg {
49: IOP3_ADD, IOP3_AND, IOP3_OR, IOP3_XOR,
50: IOP3_SUB, IOP3_ANDN, IOP3_ORN, IOP3_XNOR,
51: IOP3_ADDX, IOP3_rerr09, IOP3_UMUL, IOP3_SMUL,
52: IOP3_SUBX, IOP3_rerr0d, IOP3_UDIV, IOP3_SDIV,
53: IOP3_ADDcc, IOP3_ANDcc, IOP3_ORcc, IOP3_XORcc,
54: IOP3_SUBcc, IOP3_ANDNcc, IOP3_ORNcc, IOP3_XNORcc,
55: IOP3_ADDXcc, IOP3_rerr19, IOP3_UMULcc, IOP3_SMULcc,
56: IOP3_SUBXcc, IOP3_rerr1d, IOP3_UDIVcc, IOP3_SDIVcc,
57: IOP3_TADDcc, IOP3_TSUBcc, IOP3_TADDccTV, IOP3_TSUBccTV,
58: IOP3_MULScc, IOP3_SLL, IOP3_SRL, IOP3_SRA,
59: IOP3_RDASR_RDY_STBAR, IOP3_RDPSR, IOP3_RDWIM, IOP3_RDTGBR,
60: IOP3_rerr2c, IOP3_rerr2d, IOP3_rerr2e, IOP3_rerr2f,
61: IOP3_WRASR_WRY, IOP3_WRPSR, IOP3_WRWIM, IOP3_WRTBR,
62: IOP3_FPop1, IOP3_FPop2, IOP3_CPop1, IOP3_CPop2,
63: IOP3_JMPL, IOP3_RETT, IOP3_Ticc, IOP3_FLUSH,
64: IOP3_SAVE, IOP3_RESTORE, IOP3_rerr3e, IOP3_rerr3f
65: };
66: enum IOP3_mem {
67: IOP3_LD, IOP3_LDUB, IOP3_LDUH, IOP3_LDD,
68: IOP3_ST, IOP3_STB, IOP3_STH, IOP3_STD,
69: IOP3_merr08, IOP3_LDSB, IOP3_LDSH, IOP3_merr0b,
70: IOP3_merr0c, IOP3_LDSTUB, IOP3_merr0f, IOP3_SWAP,
71: IOP3_LDA, IOP3_LDUBA, IOP3_LDUHA, IOP3_LDDA,
72: IOP3_STA, IOP3_STBA, IOP3_STHA, IOP3_STDA,
73: IOP3_merr18, IOP3_LDSBA, IOP3_LDSHA, IOP3_merr1b,
74: IOP3_merr1c, IOP3_LDSTUBA, IOP3_merr1f, IOP3_SWAPA,
75: IOP3_LDF, IOP3_LDFSR, IOP3_merr22, IOP3_LDDF,
76: IOP3_STF, IOP3_STFSR, IOP3_STDFQ, IOP3_STDF,
77: IOP3_merr28, IOP3_merr29, IOP3_merr2a, IOP3_merr2b,
78: IOP3_merr2c, IOP3_merr2d, IOP3_merr2e, IOP3_merr2f,
79: IOP3_LFC, IOP3_LDCSR, IOP3_merr32, IOP3_LDDC,
80: IOP3_STC, IOP3_STCSR, IOP3_STDCQ, IOP3_STDC,
81: IOP3_merr38, IOP3_merr39, IOP3_merr3a, IOP3_merr3b,
82: IOP3_merr3c, IOP3_merr3d, IOP3_merr3e, IOP3_merr3f
83: };
84:
85: /*
86: * Integer condition codes.
87: */
88: #define Icc_N 0x0 /* never */
89: #define Icc_E 0x1 /* equal (equiv. zero) */
90: #define Icc_LE 0x2 /* less or equal */
91: #define Icc_L 0x3 /* less */
92: #define Icc_LEU 0x4 /* less or equal unsigned */
93: #define Icc_CS 0x5 /* carry set (equiv. less unsigned) */
94: #define Icc_NEG 0x6 /* negative */
95: #define Icc_VS 0x7 /* overflow set */
96: #define Icc_A 0x8 /* always */
97: #define Icc_NE 0x9 /* not equal (equiv. not zero) */
98: #define Icc_G 0xa /* greater */
99: #define Icc_GE 0xb /* greater or equal */
100: #define Icc_GU 0xc /* greater unsigned */
101: #define Icc_CC 0xd /* carry clear (equiv. gtr or eq unsigned) */
102: #define Icc_POS 0xe /* positive */
103: #define Icc_VC 0xf /* overflow clear */
104:
105: /*
106: * Integer registers.
107: */
108: #define I_G0 0
109: #define I_G1 1
110: #define I_G2 2
111: #define I_G3 3
112: #define I_G4 4
113: #define I_G5 5
114: #define I_G6 6
115: #define I_G7 7
116: #define I_O0 8
117: #define I_O1 9
118: #define I_O2 10
119: #define I_O3 11
120: #define I_O4 12
121: #define I_O5 13
122: #define I_O6 14
123: #define I_O7 15
124: #define I_L0 16
125: #define I_L1 17
126: #define I_L2 18
127: #define I_L3 19
128: #define I_L4 20
129: #define I_L5 21
130: #define I_L6 22
131: #define I_L7 23
132: #define I_I0 24
133: #define I_I1 25
134: #define I_I2 26
135: #define I_I3 27
136: #define I_I4 28
137: #define I_I5 29
138: #define I_I6 30
139: #define I_I7 31
140:
141: /*
142: * An instruction.
143: */
144: union instr {
145: int i_int; /* as a whole */
146:
147: /*
148: * The first level of decoding is to use the top 2 bits.
149: * This gives us one of three `formats', which usually give
150: * a second level of decoding.
151: */
152: struct {
153: u_int i_op:2; /* first-level decode */
154: u_int :30;
155: } i_any;
156:
157: /*
158: * Format 1 instructions: CALL (undifferentiated).
159: */
160: struct {
161: u_int :2; /* 01 */
162: int i_disp:30; /* displacement */
163: } i_call;
164:
165: /*
166: * Format 2 instructions (SETHI, UNIMP, and branches, plus illegal
167: * unused codes).
168: */
169: struct {
170: u_int :2; /* 00 */
171: u_int :5;
172: u_int i_op2:3; /* second-level decode */
173: u_int :22;
174: } i_op2;
175:
176: /* UNIMP, SETHI */
177: struct {
178: u_int :2; /* 00 */
179: u_int i_rd:5; /* destination register */
180: u_int i_op2:3; /* opcode: UNIMP or SETHI */
181: u_int i_imm:22; /* immediate value */
182: } i_imm22;
183:
184: /* branches: Bicc, FBfcc, CBccc */
185: struct {
186: u_int :2; /* 00 */
187: u_int i_annul:1; /* annul bit */
188: u_int i_cond:4; /* condition codes */
189: u_int i_op2:3; /* opcode: {Bi,FBf,CBc}cc */
190: int i_disp:22; /* branch displacement */
191: } i_branch;
192:
193: /*
194: * Format 3 instructions (memory reference; arithmetic, logical,
195: * shift, and other miscellaneous operations). The second-level
196: * decode almost always makes use of an `rd' and `rs1', however
197: * (see also IOP3_reg and IOP3_mem).
198: *
199: * Beyond that, the low 14 bits may be broken up in one of three
200: * different ways, if at all:
201: * 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem]
202: * 1 bit of imm=1 + 13 bits of signed immediate [reg & mem]
203: * 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only]
204: */
205: struct {
206: u_int :2; /* 10 or 11 */
207: u_int i_rd:5; /* destination register */
208: u_int i_op3:6; /* second-level decode */
209: u_int i_rs1:5; /* source register 1 */
210: u_int i_low14:14; /* varies */
211: } i_op3;
212:
213: /*
214: * Memory forms. These set i_op=3 and use simm13 or asi layout.
215: * Memory references without an ASI should use 0, but the actual
216: * ASI field is simply ignored.
217: */
218: struct {
219: u_int :2; /* 11 only */
220: u_int i_rd:5; /* destination register */
221: u_int i_op3:6; /* second-level decode (see IOP3_mem) */
222: u_int i_rs1:5; /* source register 1 */
223: u_int i_i:1; /* immediate vs asi */
224: u_int i_low13:13; /* depend on i bit */
225: } i_loadstore;
226:
227: /*
228: * Memory and register forms.
229: * These come in quite a variety and we do not
230: * attempt to break them down much.
231: */
232: struct {
233: u_int :2; /* 10 or 11 */
234: u_int i_rd:5; /* destination register */
235: u_int i_op3:6; /* second-level decode */
236: u_int i_rs1:5; /* source register 1 */
237: u_int i_i:1; /* immediate bit (1) */
238: int i_simm13:13; /* signed immediate */
239: } i_simm13;
240: struct {
241: u_int :2; /* 10 or 11 */
242: u_int i_rd:5; /* destination register */
243: u_int i_op3:6; /* second-level decode */
244: u_int i_rs1:5; /* source register 1 */
245: u_int i_i:1; /* immediate vs asi */
246: u_int i_asi:8; /* asi */
247: u_int i_rs2:5; /* source register 2 */
248: } i_asi;
249: struct {
250: u_int :2; /* 10 only (register, no memory) */
251: u_int i_rd:5; /* destination register */
252: u_int i_op3:6; /* second-level decode (see IOP3_reg) */
253: u_int i_rs1:5; /* source register 1 */
254: u_int i_opf:9; /* coprocessor 3rd-level decode */
255: u_int i_rs2:5; /* source register 2 */
256: } i_opf;
257:
258: };
259:
260: /*
261: * Internal macros for building instructions. These correspond 1-to-1 to
262: * the names above. Note that x << y | z == (x << y) | z.
263: */
264: #define _I_ANY(op, b) ((op) << 30 | (b))
265:
266: #define _I_OP2(high, op2, low) \
267: _I_ANY(IOP_OP2, (high) << 25 | (op2) << 22 | (low))
268: #define _I_IMM22(rd, op2, imm) \
269: _I_ANY(IOP_OP2, (rd) << 25 | (op2) << 22 | (imm))
270: #define _I_BRANCH(a, c, op2, disp) \
271: _I_ANY(IOP_OP2, (a) << 29 | (c) << 25 | (op2) << 22 | (disp))
272: #define _I_FBFCC(a, cond, disp) \
273: _I_BRANCH(a, cond, IOP2_FBfcc, disp)
274: #define _I_CBCCC(a, cond, disp) \
275: _I_BRANCH(a, cond, IOP2_CBccc, disp)
276:
277: #define _I_SIMM(simm) (1 << 13 | ((simm) & 0x1fff))
278:
279: #define _I_OP3_GEN(form, rd, op3, rs1, low14) \
280: _I_ANY(form, (rd) << 25 | (op3) << 19 | (rs1) << 14 | (low14))
281: #define _I_OP3_LS_RAR(rd, op3, rs1, asi, rs2) \
282: _I_OP3_GEN(IOP_mem, rd, op3, rs1, (asi) << 5 | (rs2))
283: #define _I_OP3_LS_RI(rd, op3, rs1, simm13) \
284: _I_OP3_GEN(IOP_mem, rd, op3, rs1, _I_SIMM(simm13))
285: #define _I_OP3_LS_RR(rd, op3, rs1, rs2) \
286: _I_OP3_GEN(IOP_mem, rd, op3, rs1, rs2)
287: #define _I_OP3_R_RAR(rd, op3, rs1, asi, rs2) \
288: _I_OP3_GEN(IOP_reg, rd, op3, rs1, (asi) << 5 | (rs2))
289: #define _I_OP3_R_RI(rd, op3, rs1, simm13) \
290: _I_OP3_GEN(IOP_reg, rd, op3, rs1, _I_SIMM(simm13))
291: #define _I_OP3_R_RR(rd, op3, rs1, rs2) \
292: _I_OP3_GEN(IOP_reg, rd, op3, rs1, rs2)
293:
294: #define I_CALL(d) _I_ANY(IOP_CALL, d)
295: #define I_UNIMP(v) _I_IMM22(0, IOP2_UNIMP, v)
296: #define I_BN(a, d) _I_BRANCH(a, Icc_N, IOP2_Bicc, d)
297: #define I_BE(a, d) _I_BRANCH(a, Icc_E, IOP2_Bicc, d)
298: #define I_BZ(a, d) _I_BRANCH(a, Icc_E, IOP2_Bicc, d)
299: #define I_BLE(a, d) _I_BRANCH(a, Icc_LE, IOP2_Bicc, d)
300: #define I_BL(a, d) _I_BRANCH(a, Icc_L, IOP2_Bicc, d)
301: #define I_BLEU(a, d) _I_BRANCH(a, Icc_LEU, IOP2_Bicc, d)
302: #define I_BCS(a, d) _I_BRANCH(a, Icc_CS, IOP2_Bicc, d)
303: #define I_BLU(a, d) _I_BRANCH(a, Icc_CS, IOP2_Bicc, d)
304: #define I_BNEG(a, d) _I_BRANCH(a, Icc_NEG, IOP2_Bicc, d)
305: #define I_BVS(a, d) _I_BRANCH(a, Icc_VS, IOP2_Bicc, d)
306: #define I_BA(a, d) _I_BRANCH(a, Icc_A, IOP2_Bicc, d)
307: #define I_B(a, d) _I_BRANCH(a, Icc_A, IOP2_Bicc, d)
308: #define I_BNE(a, d) _I_BRANCH(a, Icc_NE, IOP2_Bicc, d)
309: #define I_BNZ(a, d) _I_BRANCH(a, Icc_NE, IOP2_Bicc, d)
310: #define I_BG(a, d) _I_BRANCH(a, Icc_G, IOP2_Bicc, d)
311: #define I_BGE(a, d) _I_BRANCH(a, Icc_GE, IOP2_Bicc, d)
312: #define I_BGU(a, d) _I_BRANCH(a, Icc_GU, IOP2_Bicc, d)
313: #define I_BCC(a, d) _I_BRANCH(a, Icc_CC, IOP2_Bicc, d)
314: #define I_BGEU(a, d) _I_BRANCH(a, Icc_CC, IOP2_Bicc, d)
315: #define I_BPOS(a, d) _I_BRANCH(a, Icc_POS, IOP2_Bicc, d)
316: #define I_BVC(a, d) _I_BRANCH(a, Icc_VC, IOP2_Bicc, d)
317: #define I_SETHI(r, v) _I_IMM22(r, 4, v)
318:
319: #define I_ORri(rd, rs1, imm) _I_OP3_R_RI(rd, IOP3_OR, rs1, imm)
320: #define I_ORrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_OR, rs1, rs2)
321:
322: #define I_MOVi(rd, imm) _I_OP3_R_RI(rd, IOP3_OR, I_G0, imm)
323: #define I_MOVr(rd, rs) _I_OP3_R_RR(rd, IOP3_OR, I_G0, rs)
324:
325: #define I_RDPSR(rd) _I_OP3_R_RR(rd, IOP3_RDPSR, 0, 0)
326:
327: #define I_JMPLri(rd, rs1, imm) _I_OP3_R_RI(rd, IOP3_JMPL, rs1, imm)
328: #define I_JMPLrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_JMPL, rs1, rs2)
329:
330: /*
331: * (Since these are sparse, we skip the enumerations for now.)
332: * FPop values. All appear in both FPop1 and FPop2 spaces, but arithmetic
333: * ops should happen only with FPop1 and comparison only with FPop2.
334: * The type sits in the low two bits; those bits are given as zero here.
335: */
336: #define FMOV 0x00
337: #define FNEG 0x04
338: #define FABS 0x08
339: #define FSQRT 0x28
340: #define FADD 0x40
341: #define FSUB 0x44
342: #define FMUL 0x48
343: #define FDIV 0x4c
344: #define FCMP 0x50
345: #define FCMPE 0x54
346: #define FSMULD 0x68
347: #define FDMULX 0x6c
348: #define FTOS 0xc4
349: #define FTOD 0xc8
350: #define FTOX 0xcc
351: #define FTOI 0xd0
352:
353: /*
354: * FPU data types.
355: */
356: #define FTYPE_INT 0 /* data = 32-bit signed integer */
357: #define FTYPE_SNG 1 /* data = 32-bit float */
358: #define FTYPE_DBL 2 /* data = 64-bit double */
359: #define FTYPE_EXT 3 /* data = 128-bit extended (quad-prec) */
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