Annotation of sys/arch/sparc/include/cpu.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cpu.h,v 1.29 2007/05/08 07:23:18 art Exp $ */
2: /* $NetBSD: cpu.h,v 1.24 1997/03/15 22:25:15 pk Exp $ */
3:
4: /*
5: * Copyright (c) 1992, 1993
6: * The Regents of the University of California. All rights reserved.
7: *
8: * This software was developed by the Computer Systems Engineering group
9: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10: * contributed to Berkeley.
11: *
12: * All advertising materials mentioning features or use of this software
13: * must display the following acknowledgement:
14: * This product includes software developed by the University of
15: * California, Lawrence Berkeley Laboratory.
16: *
17: * Redistribution and use in source and binary forms, with or without
18: * modification, are permitted provided that the following conditions
19: * are met:
20: * 1. Redistributions of source code must retain the above copyright
21: * notice, this list of conditions and the following disclaimer.
22: * 2. Redistributions in binary form must reproduce the above copyright
23: * notice, this list of conditions and the following disclaimer in the
24: * documentation and/or other materials provided with the distribution.
25: * 3. Neither the name of the University nor the names of its contributors
26: * may be used to endorse or promote products derived from this software
27: * without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39: * SUCH DAMAGE.
40: *
41: * @(#)cpu.h 8.4 (Berkeley) 1/5/94
42: */
43:
44: #ifndef _SPARC_CPU_H_
45: #define _SPARC_CPU_H_
46:
47: /*
48: * CTL_MACHDEP definitions.
49: */
50: #define CPU_LED_BLINK 1 /* int: twiddle the power LED */
51: /* 2 formerly int: vsyncblank */
52: #define CPU_CPUTYPE 3 /* int: cpu type */
53: #define CPU_V8MUL 4
54: #define CPU_MAXID 5 /* 4 valid machdep IDs */
55:
56: #define CTL_MACHDEP_NAMES { \
57: { 0, 0 }, \
58: { "led_blink", CTLTYPE_INT }, \
59: { 0, 0 }, \
60: { "cputype", CTLTYPE_INT }, \
61: { "v8mul", CTLTYPE_INT }, \
62: }
63:
64: #ifdef _KERNEL
65: /*
66: * Exported definitions unique to SPARC cpu support.
67: */
68:
69: #include <sys/evcount.h>
70: #include <machine/psl.h>
71: #include <machine/reg.h>
72: #include <sparc/sparc/intreg.h>
73: #include <sparc/sparc/cpuvar.h>
74:
75: /*
76: * definitions of cpu-dependent requirements
77: * referenced in generic code
78: */
79: #define cpu_wait(p) /* nothing */
80:
81: /*
82: * Arguments to hardclock, softclock and gatherstats encapsulate the
83: * previous machine state in an opaque clockframe. The ipl is here
84: * as well for strayintr (see locore.s:interrupt and intr.c:strayintr).
85: * Note that CLKF_INTR is valid only if CLKF_USERMODE is false.
86: */
87: struct clockframe {
88: u_int psr; /* psr before interrupt, excluding PSR_ET */
89: u_int pc; /* pc at interrupt */
90: u_int npc; /* npc at interrupt */
91: u_int ipl; /* actual interrupt priority level */
92: u_int fp; /* %fp at interrupt */
93: };
94: typedef struct clockframe clockframe;
95:
96: extern int eintstack[];
97:
98: #define CLKF_USERMODE(framep) (((framep)->psr & PSR_PS) == 0)
99: #define CLKF_PC(framep) ((framep)->pc)
100: #define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack)
101:
102: /*
103: * Software interrupt request `register'.
104: */
105: union sir {
106: int sir_any;
107: char sir_which[4];
108: };
109: extern union sir sir;
110:
111: #define SIR_NET 0
112: #define SIR_CLOCK 1
113:
114: #if defined(SUN4M)
115: extern void raise(int, int);
116: #if !(defined(SUN4) || defined(SUN4C))
117: #define setsoftint() raise(0,1)
118: #else /* both defined */
119: #define setsoftint() (cputyp == CPU_SUN4M ? raise(0,1) : ienab_bis(IE_L1))
120: #endif /* !4,!4c */
121: #else /* 4m not defined */
122: #define setsoftint() ienab_bis(IE_L1)
123: #endif /* SUN4M */
124:
125: #define setsoftnet() (sir.sir_which[SIR_NET] = 1, setsoftint())
126: #define setsoftclock() (sir.sir_which[SIR_CLOCK] = 1, setsoftint())
127:
128: /*
129: * Preempt the current process if in interrupt from user mode,
130: * or after the current trap/syscall if in system mode.
131: */
132: extern int want_resched; /* resched() was called */
133: #define need_resched(ci) (want_resched = 1, want_ast = 1)
134: extern int want_ast;
135:
136: /*
137: * This is used during profiling to integrate system time.
138: */
139: #define PROC_PC(p) ((p)->p_md.md_tf->tf_pc)
140:
141: /*
142: * Give a profiling tick to the current process when the user profiling
143: * buffer pages are invalid. On the sparc, request an ast to send us
144: * through trap(), marking the proc as needing a profiling tick.
145: */
146: #define need_proftick(p) do { want_ast = 1; } while (0)
147:
148: /*
149: * Notify the current process (p) that it has a signal pending,
150: * process as soon as possible.
151: */
152: #define signotify(p) (want_ast = 1)
153:
154: extern int foundfpu; /* true => we have an FPU */
155:
156: /*
157: * Interrupt handler chains. Interrupt handlers should return 0 for
158: * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a
159: * handler into the list. The handler is called with its (single)
160: * argument, or with a pointer to a clockframe if ih_arg is NULL.
161: * ih_ipl specifies the interrupt level that should be blocked when
162: * executing this handler.
163: */
164: struct intrhand {
165: int (*ih_fun)(void *);
166: void *ih_arg;
167: int ih_ipl;
168: int ih_vec; /* human readable ipl for vmstat */
169: struct evcount ih_count;
170: struct intrhand *ih_next;
171: };
172: extern struct intrhand *intrhand[15];
173: void intr_establish(int level, struct intrhand *, int, const char *);
174: void vmeintr_establish(int vec, int level, struct intrhand *, int, const char *);
175:
176: /*
177: * intr_fasttrap() is a lot like intr_establish, but is used for ``fast''
178: * interrupt vectors (vectors that are not shared and are handled in the
179: * trap window). Such functions must be written in assembly.
180: */
181: int intr_fasttrap(int, void (*)(void), int (*)(void *), void *);
182: void intr_fastuntrap(int);
183:
184: /* auxreg.c */
185: void led_blink(void *);
186: /* scf.c */
187: void scfblink(void *);
188: /* disksubr.c */
189: struct dkbad;
190: int isbad(struct dkbad *bt, int, int, int);
191: /* machdep.c */
192: int ldcontrolb(caddr_t);
193: void dumpconf(void);
194: void intr_init(void);
195: caddr_t reserve_dumppages(caddr_t);
196: /* clock.c */
197: struct timeval;
198: void lo_microtime(struct timeval *);
199: int statintr(void *);
200: int clockintr(void *);/* level 10 (clock) interrupt code */
201: int statintr(void *); /* level 14 (statclock) interrupt code */
202: /* locore.s */
203: struct fpstate;
204: void savefpstate(struct fpstate *);
205: void loadfpstate(struct fpstate *);
206: int probeget(caddr_t, int);
207: void write_all_windows(void);
208: void write_user_windows(void);
209: void proc_trampoline(void);
210: struct pcb;
211: void snapshot(struct pcb *);
212: struct frame *getfp(void);
213: int xldcontrolb(caddr_t, struct pcb *);
214: void copywords(const void *, void *, size_t);
215: void qcopy(const void *, void *, size_t);
216: void qzero(void *, size_t);
217: /* locore2.c */
218: void remrunqueue(struct proc *);
219: /* trap.c */
220: void pmap_unuse_final(struct proc *);
221: int rwindow_save(struct proc *);
222: /* amd7930intr.s */
223: void amd7930_trap(void);
224: #ifdef KGDB
225: /* zs_kgdb.c */
226: void zs_kgdb_init(void);
227: #endif
228: /* fb.c */
229: void fb_unblank(void);
230: /* cache.c */
231: void cache_flush(caddr_t, u_int);
232: /* kgdb_stub.c */
233: #ifdef KGDB
234: void kgdb_attach(int (*)(void *), void (*)(void *, int), void *);
235: void kgdb_connect(int);
236: void kgdb_panic(void);
237: #endif
238: /* iommu.c */
239: void iommu_enter(u_int, u_int);
240: void iommu_remove(u_int, u_int);
241: /* emul.c */
242: struct trapframe;
243: int fixalign(struct proc *, struct trapframe *);
244: int emulinstr(int, struct trapframe *);
245:
246: /*
247: *
248: * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits
249: * of the trap vector table. The next eight bits are supplied by the
250: * hardware when the trap occurs, and the bottom four bits are always
251: * zero (so that we can shove up to 16 bytes of executable code---exactly
252: * four instructions---into each trap vector).
253: *
254: * The hardware allocates half the trap vectors to hardware and half to
255: * software.
256: *
257: * Traps have priorities assigned (lower number => higher priority).
258: */
259:
260: struct trapvec {
261: int tv_instr[4]; /* the four instructions */
262: };
263: extern struct trapvec *trapbase; /* the 256 vectors */
264:
265: #endif /* _KERNEL */
266: #endif /* _SPARC_CPU_H_ */
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