Annotation of sys/arch/sparc/fpu/fpu_implode.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: fpu_implode.c,v 1.5 2003/06/02 23:27:54 millert Exp $ */
2: /* $NetBSD: fpu_implode.c,v 1.3 1996/03/14 19:41:59 christos Exp $ */
3:
4: /*
5: * Copyright (c) 1992, 1993
6: * The Regents of the University of California. All rights reserved.
7: *
8: * This software was developed by the Computer Systems Engineering group
9: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
10: * contributed to Berkeley.
11: *
12: * All advertising materials mentioning features or use of this software
13: * must display the following acknowledgement:
14: * This product includes software developed by the University of
15: * California, Lawrence Berkeley Laboratory.
16: *
17: * Redistribution and use in source and binary forms, with or without
18: * modification, are permitted provided that the following conditions
19: * are met:
20: * 1. Redistributions of source code must retain the above copyright
21: * notice, this list of conditions and the following disclaimer.
22: * 2. Redistributions in binary form must reproduce the above copyright
23: * notice, this list of conditions and the following disclaimer in the
24: * documentation and/or other materials provided with the distribution.
25: * 3. Neither the name of the University nor the names of its contributors
26: * may be used to endorse or promote products derived from this software
27: * without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39: * SUCH DAMAGE.
40: *
41: * @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93
42: */
43:
44: /*
45: * FPU subroutines: `implode' internal format numbers into the machine's
46: * `packed binary' format.
47: */
48:
49: #include <sys/types.h>
50: #include <sys/systm.h>
51:
52: #include <machine/ieee.h>
53: #include <machine/instr.h>
54: #include <machine/reg.h>
55:
56: #include <sparc/fpu/fpu_arith.h>
57: #include <sparc/fpu/fpu_emu.h>
58: #include <sparc/fpu/fpu_extern.h>
59:
60: static int round(register struct fpemu *, register struct fpn *);
61: static int toinf(struct fpemu *, int);
62:
63: /*
64: * Round a number (algorithm from Motorola MC68882 manual, modified for
65: * our internal format). Set inexact exception if rounding is required.
66: * Return true iff we rounded up.
67: *
68: * After rounding, we discard the guard and round bits by shifting right
69: * 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
70: * This saves effort later.
71: *
72: * Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
73: * responsibility to fix this if necessary.
74: */
75: static int
76: round(register struct fpemu *fe, register struct fpn *fp)
77: {
78: register u_int m0, m1, m2, m3;
79: register int gr, s;
80:
81: m0 = fp->fp_mant[0];
82: m1 = fp->fp_mant[1];
83: m2 = fp->fp_mant[2];
84: m3 = fp->fp_mant[3];
85: gr = m3 & 3;
86: s = fp->fp_sticky;
87:
88: /* mant >>= FP_NG */
89: m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
90: m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
91: m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
92: m0 >>= FP_NG;
93:
94: if ((gr | s) == 0) /* result is exact: no rounding needed */
95: goto rounddown;
96:
97: fe->fe_cx |= FSR_NX; /* inexact */
98:
99: /* Go to rounddown to round down; break to round up. */
100: switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) {
101:
102: case FSR_RD_RN:
103: default:
104: /*
105: * Round only if guard is set (gr & 2). If guard is set,
106: * but round & sticky both clear, then we want to round
107: * but have a tie, so round to even, i.e., add 1 iff odd.
108: */
109: if ((gr & 2) == 0)
110: goto rounddown;
111: if ((gr & 1) || fp->fp_sticky || (m3 & 1))
112: break;
113: goto rounddown;
114:
115: case FSR_RD_RZ:
116: /* Round towards zero, i.e., down. */
117: goto rounddown;
118:
119: case FSR_RD_RM:
120: /* Round towards -Inf: up if negative, down if positive. */
121: if (fp->fp_sign)
122: break;
123: goto rounddown;
124:
125: case FSR_RD_RP:
126: /* Round towards +Inf: up if positive, down otherwise. */
127: if (!fp->fp_sign)
128: break;
129: goto rounddown;
130: }
131:
132: /* Bump low bit of mantissa, with carry. */
133: #ifdef sparc /* ``cheating'' (left out FPU_DECL_CARRY; know this is faster) */
134: FPU_ADDS(m3, m3, 1);
135: FPU_ADDCS(m2, m2, 0);
136: FPU_ADDCS(m1, m1, 0);
137: FPU_ADDC(m0, m0, 0);
138: #else
139: if (++m3 == 0 && ++m2 == 0 && ++m1 == 0)
140: m0++;
141: #endif
142: fp->fp_mant[0] = m0;
143: fp->fp_mant[1] = m1;
144: fp->fp_mant[2] = m2;
145: fp->fp_mant[3] = m3;
146: return (1);
147:
148: rounddown:
149: fp->fp_mant[0] = m0;
150: fp->fp_mant[1] = m1;
151: fp->fp_mant[2] = m2;
152: fp->fp_mant[3] = m3;
153: return (0);
154: }
155:
156: /*
157: * For overflow: return true if overflow is to go to +/-Inf, according
158: * to the sign of the overflowing result. If false, overflow is to go
159: * to the largest magnitude value instead.
160: */
161: static int
162: toinf(struct fpemu *fe, int sign)
163: {
164: int inf;
165:
166: /* look at rounding direction */
167: switch ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK) {
168:
169: default:
170: case FSR_RD_RN: /* the nearest value is always Inf */
171: inf = 1;
172: break;
173:
174: case FSR_RD_RZ: /* toward 0 => never towards Inf */
175: inf = 0;
176: break;
177:
178: case FSR_RD_RP: /* toward +Inf iff positive */
179: inf = sign == 0;
180: break;
181:
182: case FSR_RD_RM: /* toward -Inf iff negative */
183: inf = sign;
184: break;
185: }
186: return (inf);
187: }
188:
189: /*
190: * fpn -> int (int value returned as return value).
191: *
192: * N.B.: this conversion always rounds towards zero (this is a peculiarity
193: * of the SPARC instruction set).
194: */
195: u_int
196: fpu_ftoi(fe, fp)
197: struct fpemu *fe;
198: register struct fpn *fp;
199: {
200: register u_int i;
201: register int sign, exp;
202:
203: sign = fp->fp_sign;
204: switch (fp->fp_class) {
205:
206: case FPC_ZERO:
207: return (0);
208:
209: case FPC_NUM:
210: /*
211: * If exp >= 2^32, overflow. Otherwise shift value right
212: * into last mantissa word (this will not exceed 0xffffffff),
213: * shifting any guard and round bits out into the sticky
214: * bit. Then ``round'' towards zero, i.e., just set an
215: * inexact exception if sticky is set (see round()).
216: * If the result is > 0x80000000, or is positive and equals
217: * 0x80000000, overflow; otherwise the last fraction word
218: * is the result.
219: */
220: if ((exp = fp->fp_exp) >= 32)
221: break;
222: /* NB: the following includes exp < 0 cases */
223: if (fpu_shr(fp, FP_NMANT - 1 - exp) != 0)
224: fe->fe_cx |= FSR_NX;
225: i = fp->fp_mant[3];
226: if (i >= ((u_int)0x80000000 + sign))
227: break;
228: return (sign ? -i : i);
229:
230: default: /* Inf, qNaN, sNaN */
231: break;
232: }
233: /* overflow: replace any inexact exception with invalid */
234: fe->fe_cx = (fe->fe_cx & ~FSR_NX) | FSR_NV;
235: return (0x7fffffff + sign);
236: }
237:
238: /*
239: * fpn -> single (32 bit single returned as return value).
240: * We assume <= 29 bits in a single-precision fraction (1.f part).
241: */
242: u_int
243: fpu_ftos(fe, fp)
244: struct fpemu *fe;
245: register struct fpn *fp;
246: {
247: register u_int sign = fp->fp_sign << 31;
248: register int exp;
249:
250: #define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */
251: #define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */
252:
253: /* Take care of non-numbers first. */
254: if (ISNAN(fp)) {
255: /*
256: * Preserve upper bits of NaN, per SPARC V8 appendix N.
257: * Note that fp->fp_mant[0] has the quiet bit set,
258: * even if it is classified as a signalling NaN.
259: */
260: (void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
261: exp = SNG_EXP_INFNAN;
262: goto done;
263: }
264: if (ISINF(fp))
265: return (sign | SNG_EXP(SNG_EXP_INFNAN));
266: if (ISZERO(fp))
267: return (sign);
268:
269: /*
270: * Normals (including subnormals). Drop all the fraction bits
271: * (including the explicit ``implied'' 1 bit) down into the
272: * single-precision range. If the number is subnormal, move
273: * the ``implied'' 1 into the explicit range as well, and shift
274: * right to introduce leading zeroes. Rounding then acts
275: * differently for normals and subnormals: the largest subnormal
276: * may round to the smallest normal (1.0 x 2^minexp), or may
277: * remain subnormal. In the latter case, signal an underflow
278: * if the result was inexact or if underflow traps are enabled.
279: *
280: * Rounding a normal, on the other hand, always produces another
281: * normal (although either way the result might be too big for
282: * single precision, and cause an overflow). If rounding a
283: * normal produces 2.0 in the fraction, we need not adjust that
284: * fraction at all, since both 1.0 and 2.0 are zero under the
285: * fraction mask.
286: *
287: * Note that the guard and round bits vanish from the number after
288: * rounding.
289: */
290: if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */
291: /* -NG for g,r; -SNG_FRACBITS-exp for fraction */
292: (void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
293: if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1))
294: return (sign | SNG_EXP(1) | 0);
295: if ((fe->fe_cx & FSR_NX) ||
296: (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
297: fe->fe_cx |= FSR_UF;
298: return (sign | SNG_EXP(0) | fp->fp_mant[3]);
299: }
300: /* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
301: (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
302: #ifdef DIAGNOSTIC
303: if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
304: panic("fpu_ftos");
305: #endif
306: if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2))
307: exp++;
308: if (exp >= SNG_EXP_INFNAN) {
309: /* overflow to inf or to max single */
310: fe->fe_cx |= FSR_OF | FSR_NX;
311: if (toinf(fe, sign))
312: return (sign | SNG_EXP(SNG_EXP_INFNAN));
313: return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
314: }
315: done:
316: /* phew, made it */
317: return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
318: }
319:
320: /*
321: * fpn -> double (32 bit high-order result returned; 32-bit low order result
322: * left in res[1]). Assumes <= 61 bits in double precision fraction.
323: *
324: * This code mimics fpu_ftos; see it for comments.
325: */
326: u_int
327: fpu_ftod(fe, fp, res)
328: struct fpemu *fe;
329: register struct fpn *fp;
330: u_int *res;
331: {
332: register u_int sign = fp->fp_sign << 31;
333: register int exp;
334:
335: #define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31))
336: #define DBL_MASK (DBL_EXP(1) - 1)
337:
338: if (ISNAN(fp)) {
339: (void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
340: exp = DBL_EXP_INFNAN;
341: goto done;
342: }
343: if (ISINF(fp)) {
344: sign |= DBL_EXP(DBL_EXP_INFNAN);
345: goto zero;
346: }
347: if (ISZERO(fp)) {
348: zero: res[1] = 0;
349: return (sign);
350: }
351:
352: if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
353: (void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
354: if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) {
355: res[1] = 0;
356: return (sign | DBL_EXP(1) | 0);
357: }
358: if ((fe->fe_cx & FSR_NX) ||
359: (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
360: fe->fe_cx |= FSR_UF;
361: exp = 0;
362: goto done;
363: }
364: (void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
365: if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2))
366: exp++;
367: if (exp >= DBL_EXP_INFNAN) {
368: fe->fe_cx |= FSR_OF | FSR_NX;
369: if (toinf(fe, sign)) {
370: res[1] = 0;
371: return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
372: }
373: res[1] = ~0;
374: return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK);
375: }
376: done:
377: res[1] = fp->fp_mant[3];
378: return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK));
379: }
380:
381: /*
382: * fpn -> extended (32 bit high-order result returned; low-order fraction
383: * words left in res[1]..res[3]). Like ftod, which is like ftos ... but
384: * our internal format *is* extended precision, plus 2 bits for guard/round,
385: * so we can avoid a small bit of work.
386: */
387: u_int
388: fpu_ftox(fe, fp, res)
389: struct fpemu *fe;
390: register struct fpn *fp;
391: u_int *res;
392: {
393: register u_int sign = fp->fp_sign << 31;
394: register int exp;
395:
396: #define EXT_EXP(e) ((e) << (EXT_FRACBITS & 31))
397: #define EXT_MASK (EXT_EXP(1) - 1)
398:
399: if (ISNAN(fp)) {
400: (void) fpu_shr(fp, 2); /* since we are not rounding */
401: exp = EXT_EXP_INFNAN;
402: goto done;
403: }
404: if (ISINF(fp)) {
405: sign |= EXT_EXP(EXT_EXP_INFNAN);
406: goto zero;
407: }
408: if (ISZERO(fp)) {
409: zero: res[1] = res[2] = res[3] = 0;
410: return (sign);
411: }
412:
413: if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) {
414: (void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp);
415: if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(1)) {
416: res[1] = res[2] = res[3] = 0;
417: return (sign | EXT_EXP(1) | 0);
418: }
419: if ((fe->fe_cx & FSR_NX) ||
420: (fe->fe_fsr & (FSR_UF << FSR_TEM_SHIFT)))
421: fe->fe_cx |= FSR_UF;
422: exp = 0;
423: goto done;
424: }
425: /* Since internal == extended, no need to shift here. */
426: if (round(fe, fp) && fp->fp_mant[0] == EXT_EXP(2))
427: exp++;
428: if (exp >= EXT_EXP_INFNAN) {
429: fe->fe_cx |= FSR_OF | FSR_NX;
430: if (toinf(fe, sign)) {
431: res[1] = res[2] = res[3] = 0;
432: return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0);
433: }
434: res[1] = res[2] = res[3] = ~0;
435: return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK);
436: }
437: done:
438: res[1] = fp->fp_mant[1];
439: res[2] = fp->fp_mant[2];
440: res[3] = fp->fp_mant[3];
441: return (sign | EXT_EXP(exp) | (fp->fp_mant[0] & EXT_MASK));
442: }
443:
444: /*
445: * Implode an fpn, writing the result into the given space.
446: */
447: void
448: fpu_implode(fe, fp, type, space)
449: struct fpemu *fe;
450: register struct fpn *fp;
451: int type;
452: register u_int *space;
453: {
454:
455: switch (type) {
456:
457: case FTYPE_INT:
458: space[0] = fpu_ftoi(fe, fp);
459: break;
460:
461: case FTYPE_SNG:
462: space[0] = fpu_ftos(fe, fp);
463: break;
464:
465: case FTYPE_DBL:
466: space[0] = fpu_ftod(fe, fp, space);
467: break;
468:
469: case FTYPE_EXT:
470: /* funky rounding precision options ?? */
471: space[0] = fpu_ftox(fe, fp, space);
472: break;
473:
474: default:
475: panic("fpu_implode");
476: }
477: }
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