Annotation of sys/arch/sparc/fpu/fpu_explode.c, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: fpu_explode.c,v 1.4 2003/06/02 23:27:54 millert Exp $ */
! 2: /* $NetBSD: fpu_explode.c,v 1.3 1996/03/14 19:41:54 christos Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1992, 1993
! 6: * The Regents of the University of California. All rights reserved.
! 7: *
! 8: * This software was developed by the Computer Systems Engineering group
! 9: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
! 10: * contributed to Berkeley.
! 11: *
! 12: * All advertising materials mentioning features or use of this software
! 13: * must display the following acknowledgement:
! 14: * This product includes software developed by the University of
! 15: * California, Lawrence Berkeley Laboratory.
! 16: *
! 17: * Redistribution and use in source and binary forms, with or without
! 18: * modification, are permitted provided that the following conditions
! 19: * are met:
! 20: * 1. Redistributions of source code must retain the above copyright
! 21: * notice, this list of conditions and the following disclaimer.
! 22: * 2. Redistributions in binary form must reproduce the above copyright
! 23: * notice, this list of conditions and the following disclaimer in the
! 24: * documentation and/or other materials provided with the distribution.
! 25: * 3. Neither the name of the University nor the names of its contributors
! 26: * may be used to endorse or promote products derived from this software
! 27: * without specific prior written permission.
! 28: *
! 29: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 30: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 31: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 32: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 33: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 37: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 38: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 39: * SUCH DAMAGE.
! 40: *
! 41: * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93
! 42: */
! 43:
! 44: /*
! 45: * FPU subroutines: `explode' the machine's `packed binary' format numbers
! 46: * into our internal format.
! 47: */
! 48:
! 49: #include <sys/types.h>
! 50: #include <sys/systm.h>
! 51:
! 52: #include <machine/ieee.h>
! 53: #include <machine/instr.h>
! 54: #include <machine/reg.h>
! 55:
! 56: #include <sparc/fpu/fpu_arith.h>
! 57: #include <sparc/fpu/fpu_emu.h>
! 58: #include <sparc/fpu/fpu_extern.h>
! 59:
! 60: /*
! 61: * N.B.: in all of the following, we assume the FP format is
! 62: *
! 63: * ---------------------------
! 64: * | s | exponent | fraction |
! 65: * ---------------------------
! 66: *
! 67: * (which represents -1**s * 1.fraction * 2**exponent), so that the
! 68: * sign bit is way at the top (bit 31), the exponent is next, and
! 69: * then the remaining bits mark the fraction. A zero exponent means
! 70: * zero or denormalized (0.fraction rather than 1.fraction), and the
! 71: * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN.
! 72: *
! 73: * Since the sign bit is always the topmost bit---this holds even for
! 74: * integers---we set that outside all the *tof functions. Each function
! 75: * returns the class code for the new number (but note that we use
! 76: * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate).
! 77: */
! 78:
! 79: /*
! 80: * int -> fpn.
! 81: */
! 82: int
! 83: fpu_itof(fp, i)
! 84: register struct fpn *fp;
! 85: register u_int i;
! 86: {
! 87:
! 88: if (i == 0)
! 89: return (FPC_ZERO);
! 90: /*
! 91: * The value FP_1 represents 2^FP_LG, so set the exponent
! 92: * there and let normalization fix it up. Convert negative
! 93: * numbers to sign-and-magnitude. Note that this relies on
! 94: * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
! 95: */
! 96: fp->fp_exp = FP_LG;
! 97: fp->fp_mant[0] = (int)i < 0 ? -i : i;
! 98: fp->fp_mant[1] = 0;
! 99: fp->fp_mant[2] = 0;
! 100: fp->fp_mant[3] = 0;
! 101: fpu_norm(fp);
! 102: return (FPC_NUM);
! 103: }
! 104:
! 105: #define mask(nbits) ((1 << (nbits)) - 1)
! 106:
! 107: /*
! 108: * All external floating formats convert to internal in the same manner,
! 109: * as defined here. Note that only normals get an implied 1.0 inserted.
! 110: */
! 111: #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \
! 112: if (exp == 0) { \
! 113: if (allfrac == 0) \
! 114: return (FPC_ZERO); \
! 115: fp->fp_exp = 1 - expbias; \
! 116: fp->fp_mant[0] = f0; \
! 117: fp->fp_mant[1] = f1; \
! 118: fp->fp_mant[2] = f2; \
! 119: fp->fp_mant[3] = f3; \
! 120: fpu_norm(fp); \
! 121: return (FPC_NUM); \
! 122: } \
! 123: if (exp == (2 * expbias + 1)) { \
! 124: if (allfrac == 0) \
! 125: return (FPC_INF); \
! 126: fp->fp_mant[0] = f0; \
! 127: fp->fp_mant[1] = f1; \
! 128: fp->fp_mant[2] = f2; \
! 129: fp->fp_mant[3] = f3; \
! 130: return (FPC_QNAN); \
! 131: } \
! 132: fp->fp_exp = exp - expbias; \
! 133: fp->fp_mant[0] = FP_1 | f0; \
! 134: fp->fp_mant[1] = f1; \
! 135: fp->fp_mant[2] = f2; \
! 136: fp->fp_mant[3] = f3; \
! 137: return (FPC_NUM)
! 138:
! 139: /*
! 140: * 32-bit single precision -> fpn.
! 141: * We assume a single occupies at most (64-FP_LG) bits in the internal
! 142: * format: i.e., needs at most fp_mant[0] and fp_mant[1].
! 143: */
! 144: int
! 145: fpu_stof(fp, i)
! 146: register struct fpn *fp;
! 147: register u_int i;
! 148: {
! 149: register int exp;
! 150: register u_int frac, f0, f1;
! 151: #define SNG_SHIFT (SNG_FRACBITS - FP_LG)
! 152:
! 153: exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);
! 154: frac = i & mask(SNG_FRACBITS);
! 155: f0 = frac >> SNG_SHIFT;
! 156: f1 = frac << (32 - SNG_SHIFT);
! 157: FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0);
! 158: }
! 159:
! 160: /*
! 161: * 64-bit double -> fpn.
! 162: * We assume this uses at most (96-FP_LG) bits.
! 163: */
! 164: int
! 165: fpu_dtof(fp, i, j)
! 166: register struct fpn *fp;
! 167: register u_int i, j;
! 168: {
! 169: register int exp;
! 170: register u_int frac, f0, f1, f2;
! 171: #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG)
! 172:
! 173: exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);
! 174: frac = i & mask(DBL_FRACBITS - 32);
! 175: f0 = frac >> DBL_SHIFT;
! 176: f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT);
! 177: f2 = j << (32 - DBL_SHIFT);
! 178: frac |= j;
! 179: FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0);
! 180: }
! 181:
! 182: /*
! 183: * 128-bit extended -> fpn.
! 184: */
! 185: int
! 186: fpu_xtof(fp, i, j, k, l)
! 187: register struct fpn *fp;
! 188: register u_int i, j, k, l;
! 189: {
! 190: register int exp;
! 191: register u_int frac, f0, f1, f2, f3;
! 192: #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */
! 193:
! 194: /*
! 195: * Note that ext and fpn `line up', hence no shifting needed.
! 196: */
! 197: exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS);
! 198: frac = i & mask(EXT_FRACBITS - 3 * 32);
! 199: f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT));
! 200: f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT));
! 201: f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT));
! 202: f3 = l << EXT_SHIFT;
! 203: frac |= j | k | l;
! 204: FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3);
! 205: }
! 206:
! 207: /*
! 208: * Explode the contents of a register / regpair / regquad.
! 209: * If the input is a signalling NaN, an NV (invalid) exception
! 210: * will be set. (Note that nothing but NV can occur until ALU
! 211: * operations are performed.)
! 212: */
! 213: void
! 214: fpu_explode(fe, fp, type, reg)
! 215: register struct fpemu *fe;
! 216: register struct fpn *fp;
! 217: int type, reg;
! 218: {
! 219: register u_int s, *space;
! 220:
! 221: space = &fe->fe_fpstate->fs_regs[reg];
! 222: s = space[0];
! 223: fp->fp_sign = s >> 31;
! 224: fp->fp_sticky = 0;
! 225: switch (type) {
! 226:
! 227: case FTYPE_INT:
! 228: s = fpu_itof(fp, s);
! 229: break;
! 230:
! 231: case FTYPE_SNG:
! 232: s = fpu_stof(fp, s);
! 233: break;
! 234:
! 235: case FTYPE_DBL:
! 236: s = fpu_dtof(fp, s, space[1]);
! 237: break;
! 238:
! 239: case FTYPE_EXT:
! 240: s = fpu_xtof(fp, s, space[1], space[2], space[3]);
! 241: break;
! 242:
! 243: default:
! 244: panic("fpu_explode");
! 245: }
! 246: if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
! 247: /*
! 248: * Input is a signalling NaN. All operations that return
! 249: * an input NaN operand put it through a ``NaN conversion'',
! 250: * which basically just means ``turn on the quiet bit''.
! 251: * We do this here so that all NaNs internally look quiet
! 252: * (we can tell signalling ones by their class).
! 253: */
! 254: fp->fp_mant[0] |= FP_QUIETBIT;
! 255: fe->fe_cx = FSR_NV; /* assert invalid operand */
! 256: s = FPC_SNAN;
! 257: }
! 258: fp->fp_class = s;
! 259: }
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