File: [local] / sys / arch / sparc / fpu / fpu_compare.c (download)
Revision 1.1.1.1 (vendor branch), Tue Mar 4 16:08:16 2008 UTC (16 years, 4 months ago) by nbrk
Branch: OPENBSD_4_2_BASE, MAIN
CVS Tags: jornada-partial-support-wip, HEAD Changes since 1.1: +0 -0 lines
Import of OpenBSD 4.2 release kernel tree with initial code to support
Jornada 720/728, StrongARM 1110-based handheld PC.
At this point kernel roots on NFS and boots into vfs_mountroot() and traps.
What is supported:
- glass console, Jornada framebuffer (jfb) works in 16bpp direct color mode
(needs some palette tweaks for non black/white/blue colors, i think)
- saic, SA11x0 interrupt controller (needs cleanup)
- sacom, SA11x0 UART (supported only as boot console for now)
- SA11x0 GPIO controller fully supported (but can't handle multiple interrupt
handlers on one gpio pin)
- sassp, SSP port on SA11x0 that attaches spibus
- Jornada microcontroller (jmcu) to control kbd, battery, etc throught
the SPI bus (wskbd attaches on jmcu, but not tested)
- tod functions seem work
- initial code for SA-1111 (chip companion) : this is TODO
Next important steps, i think:
- gpio and intc on sa1111
- pcmcia support for sa11x0 (and sa1111 help logic)
- REAL root on nfs when we have PCMCIA support (we may use any of supported pccard NICs)
- root on wd0! (using already supported PCMCIA-ATA)
|
/* $OpenBSD: fpu_compare.c,v 1.3 2003/06/02 23:27:54 millert Exp $ */
/* $NetBSD: fpu_compare.c,v 1.2 1994/11/20 20:52:37 deraadt Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)fpu_compare.c 8.1 (Berkeley) 6/11/93
*/
/*
* CMP and CMPE instructions.
*
* These rely on the fact that our internal wide format is achieved by
* adding zero bits to the end of narrower mantissas.
*/
#include <sys/types.h>
#include <machine/reg.h>
#include <sparc/fpu/fpu_arith.h>
#include <sparc/fpu/fpu_emu.h>
/*
* Perform a compare instruction (with or without unordered exception).
* This updates the fcc field in the fsr.
*
* If either operand is NaN, the result is unordered. For cmpe, this
* causes an NV exception. Everything else is ordered:
* |Inf| > |numbers| > |0|.
* We already arranged for fp_class(Inf) > fp_class(numbers) > fp_class(0),
* so we get this directly. Note, however, that two zeros compare equal
* regardless of sign, while everything else depends on sign.
*
* Incidentally, two Infs of the same sign compare equal (per the 80387
* manual---it would be nice if the SPARC documentation were more
* complete).
*/
void
fpu_compare(struct fpemu *fe, int cmpe)
{
register struct fpn *a, *b;
register int cc, r3, r2, r1, r0;
FPU_DECL_CARRY
a = &fe->fe_f1;
b = &fe->fe_f2;
if (ISNAN(a) || ISNAN(b)) {
/*
* In any case, we already got an exception for signalling
* NaNs; here we may replace that one with an identical
* exception, but so what?.
*/
if (cmpe)
fe->fe_cx = FSR_NV;
cc = FSR_CC_UO;
goto done;
}
/*
* Must handle both-zero early to avoid sign goofs. Otherwise,
* at most one is 0, and if the signs differ we are done.
*/
if (ISZERO(a) && ISZERO(b)) {
cc = FSR_CC_EQ;
goto done;
}
if (a->fp_sign) { /* a < 0 (or -0) */
if (!b->fp_sign) { /* b >= 0 (or if a = -0, b > 0) */
cc = FSR_CC_LT;
goto done;
}
} else { /* a > 0 (or +0) */
if (b->fp_sign) { /* b <= -0 (or if a = +0, b < 0) */
cc = FSR_CC_GT;
goto done;
}
}
/*
* Now the signs are the same (but may both be negative). All
* we have left are these cases:
*
* |a| < |b| [classes or values differ]
* |a| > |b| [classes or values differ]
* |a| == |b| [classes and values identical]
*
* We define `diff' here to expand these as:
*
* |a| < |b|, a,b >= 0: a < b => FSR_CC_LT
* |a| < |b|, a,b < 0: a > b => FSR_CC_GT
* |a| > |b|, a,b >= 0: a > b => FSR_CC_GT
* |a| > |b|, a,b < 0: a < b => FSR_CC_LT
*/
#define opposite_cc(cc) ((cc) == FSR_CC_LT ? FSR_CC_GT : FSR_CC_LT)
#define diff(magnitude) (a->fp_sign ? opposite_cc(magnitude) : (magnitude))
if (a->fp_class < b->fp_class) { /* |a| < |b| */
cc = diff(FSR_CC_LT);
goto done;
}
if (a->fp_class > b->fp_class) { /* |a| > |b| */
cc = diff(FSR_CC_GT);
goto done;
}
/* now none can be 0: only Inf and numbers remain */
if (ISINF(a)) { /* |Inf| = |Inf| */
cc = FSR_CC_EQ;
goto done;
}
/*
* Only numbers remain. To compare two numbers in magnitude, we
* simply subtract their mantissas.
*/
FPU_SUBS(r3, a->fp_mant[0], b->fp_mant[0]);
FPU_SUBCS(r2, a->fp_mant[1], b->fp_mant[1]);
FPU_SUBCS(r1, a->fp_mant[2], b->fp_mant[2]);
FPU_SUBC(r0, a->fp_mant[3], b->fp_mant[3]);
if (r0 < 0) /* underflow: |a| < |b| */
cc = diff(FSR_CC_LT);
else if ((r0 | r1 | r2 | r3) != 0) /* |a| > |b| */
cc = diff(FSR_CC_GT);
else
cc = FSR_CC_EQ; /* |a| == |b| */
done:
fe->fe_fsr = (fe->fe_fsr & ~FSR_FCC) | (cc << FSR_FCC_SHIFT);
}