Annotation of sys/arch/sparc/dev/vmereg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: vmereg.h,v 1.1 1997/08/08 08:25:32 downsj Exp $ */
2: /* $NetBSD: vmereg.h,v 1.2 1997/06/07 19:10:57 pk Exp $ */
3:
4: /*
5: * Copyright (c) 1997 Paul Kranenburg
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. All advertising materials mentioning features or use of this software
16: * must display the following acknowledgement:
17: * This product includes software developed by Paul Kranenburg.
18: * 4. Neither the name of the University nor the names of its contributors
19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32: * SUCH DAMAGE.
33: *
34: */
35:
36: struct vmebusreg {
37: u_int32_t vmebus_cr; /* VMEbus control register */
38: u_int32_t vmebus_afar; /* VMEbus async fault address */
39: u_int32_t vmebus_afsr; /* VMEbus async fault status */
40: };
41:
42: /* Control Register bits */
43: #define VMEBUS_CR_C 0x80000000 /* I/O cache enable */
44: #define VMEBUS_CR_S 0x40000000 /* VME slave enable */
45: #define VMEBUS_CR_L 0x20000000 /* Loopback enable (diagnostic) */
46: #define VMEBUS_CR_R 0x10000000 /* VMEbus reset */
47: #define VMEBUS_CR_RSVD 0x0ffffff0 /* reserved */
48: #define VMEBUS_CR_IMPL 0x0000000f /* VMEbus interface implementation */
49:
50: /* Asynchronous Fault Status bits */
51: #define VMEBUS_AFSR_SZ 0xe0000000 /* Error transaction size */
52: #define VMEBUS_AFSR_SZ4 0 /* 4 byte */
53: #define VMEBUS_AFSR_SZ1 1 /* 1 byte */
54: #define VMEBUS_AFSR_SZ2 2 /* 2 byte */
55: #define VMEBUS_AFSR_SZ32 5 /* 32 byte */
56: #define VMEBUS_AFSR_TO 0x10000000 /* VME master access time-out */
57: #define VMEBUS_AFSR_BERR 0x08000000 /* VME master got BERR */
58: #define VMEBUS_AFSR_WB 0x04000000 /* IOC write-back error (if SZ == 32) */
59: /* Non-IOC write error (id SZ != 32) */
60: #define VMEBUS_AFSR_ERR 0x02000000 /* Error summary bit */
61: #define VMEBUS_AFSR_S 0x01000000 /* MVME error in supervisor space */
62: #define VMEBUS_AFSR_ME 0x00800000 /* Multiple error */
63: #define VMEBUS_AFSR_RSVD 0x007fffff /* reserved */
64:
65: struct vmebusvec {
66: volatile u_int8_t vmebusvec[16];
67: };
68:
69: /* VME address modifiers */
70: #define VMEMOD_A16_D_S 0x2d /* 16-bit address, data, supervisor */
71: #define VMEMOD_A24_D_S 0x3d /* 24-bit address, data, supervisor */
72: #define VMEMOD_A32_D_S 0x0d /* 32-bit address, data, supervisor */
73:
74: #define VMEMOD_D32 0x40 /* 32-bit access */
75:
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