Annotation of sys/arch/sparc/dev/ts102reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ts102reg.h,v 1.7 2005/07/08 12:35:15 miod Exp $ */
2: /* $NetBSD: ts102reg.h,v 1.7 2002/09/29 23:23:58 wiz Exp $ */
3:
4: /*-
5: * Copyright (c) 1998 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by Matt Thomas.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
38: */
39: #ifndef _SPARC_DEV_TS102REG_H
40: #define _SPARC_DEV_TS102REG_H
41:
42: /* The TS102 consumes a 256MB region of the SPARCbook 3's address space.
43: */
44: #define TS102_OFFSET_REGISTERS 0x02000000
45: #define TS102_OFFSET_CARD_A_ATTR_SPACE 0x04000000
46: #define TS102_OFFSET_CARD_B_ATTR_SPACE 0x05000000
47: #define TS102_SIZE_ATTR_SPACE 0x01000000
48: #define TS102_OFFSET_CARD_A_IO_SPACE 0x06000000
49: #define TS102_OFFSET_CARD_B_IO_SPACE 0x07000000
50: #define TS102_SIZE_IO_SPACE 0x01000000
51: #define TS102_OFFSET_CARD_A_MEM_SPACE 0x08000000
52: #define TS102_OFFSET_CARD_B_MEM_SPACE 0x0c000000
53: #define TS102_SIZE_MEM_SPACE 0x04000000
54:
55: /* There are two separate register blocks within the TS102. The first
56: * gives access to PCMCIA card specific resources, and the second gives
57: * access to the microcontroller interface
58: */
59: #define TS102_REG_CARD_A_INT 0x0000 /* Card A Interrupt Register */
60: #define TS102_REG_CARD_A_STS 0x0004 /* Card A Status Register */
61: #define TS102_REG_CARD_A_CTL 0x0008 /* Card A Control Register */
62: #define TS102_REG_CARD_B_INT 0x0010 /* Card B Interrupt Register */
63: #define TS102_REG_CARD_B_STS 0x0014 /* Card B Status Register */
64: #define TS102_REG_CARD_B_CTL 0x0018 /* Card B Control Register */
65: #define TS102_REG_UCTRL_INT 0x0020 /* Microcontroller Interrupt Register */
66: #define TS102_REG_UCTRL_DATA 0x0024 /* Microcontroller Data Register */
67: #define TS102_REG_UCTRL_STS 0x0028 /* Microcontroller Status Register */
68:
69: struct uctrl_regs {
70: volatile u_int8_t intr; /* Microcontroller Interrupt Reg */
71: volatile u_int8_t filler0[3];
72: volatile u_int8_t data; /* Microcontroller Data Reg */
73: volatile u_int8_t filler1[3];
74: volatile u_int8_t stat; /* Microcontroller Status Reg */
75: volatile u_int8_t filler2[3];
76: };
77:
78: /* TS102 Card Interrupt Register definitions.
79: *
80: * There is one 16-bit interrupt register for each card. Each register
81: * contains interrupt status (read) and clear (write) bits and an
82: * interrupt mask for each of the four interrupt sources.
83: *
84: * The request bit is the logical AND of the status and the mask bit,
85: * and indicated and an interrupt is being requested. The mask bits
86: * allow masking of individual interrupts. An interrupt is enabled when
87: * the mask is set to 1 and is clear by write a 1 to the associated
88: * request bit.
89: *
90: * The card interrupt register also contain the soft reset flag.
91: * Setting this bit to 1 will the SPARCbook 3 to be reset.
92: */
93: #define TS102_CARD_INT_RQST_IRQ 0x0001
94: #define TS102_CARD_INT_RQST_WP_STATUS_CHANGED 0x0002
95: #define TS102_CARD_INT_RQST_BATTERY_STATUS_CHANGED 0x0004
96: #define TS102_CARD_INT_RQST_CARDDETECT_STATUS_CHANGED 0x0008
97: #define TS102_CARD_INT_STATUS_IRQ 0x0010
98: #define TS102_CARD_INT_STATUS_WP_STATUS_CHANGED 0x0020
99: #define TS102_CARD_INT_STATUS_BATTERY_STATUS_CHANGED 0x0040
100: #define TS102_CARD_INT_STATUS_CARDDETECT_STATUS_CHANGED 0x0080
101: #define TS102_CARD_INT_MASK_IRQ 0x0100
102: #define TS102_CARD_INT_MASK_WP_STATUS 0x0200
103: #define TS102_CARD_INT_MASK_BATTERY_STATUS 0x0400
104: #define TS102_CARD_INT_MASK_CARDDETECT_STATUS 0x0800
105: #define TS102_CARD_INT_SOFT_RESET 0x1000
106:
107: /* TS102 Card Status Register definitions. The Card Status Register
108: * contains card status and control bit.
109: */
110: #define TS102_CARD_STS_PRES 0x0001 /* Card Present (1) */
111: #define TS102_CARD_STS_IO 0x0002 /* (1) I/O Card, (0) = Mem Card */
112: #define TS102_CARD_STS_TYPE3 0x0004 /* Type-3 PCMCIA card (disk) */
113: #define TS102_CARD_STS_VCC 0x0008 /* Vcc (0=5V, 1=3.3V) */
114: #define TS102_CARD_STS_VPP1_MASK 0x0030 /* Programming Voltage Control2 */
115: #define TS102_CARD_STS_VPP1_NC 0x0030 /* NC */
116: #define TS102_CARD_STS_VPP1_VCC 0x0020 /* Vcc (3.3V or 5V) */
117: #define TS102_CARD_STS_VPP1_VPP 0x0010 /* Vpp (12V) */
118: #define TS102_CARD_STS_VPP1_0V 0x0000 /* 0V */
119: #define TS102_CARD_STS_VPP2_MASK 0x00c0 /* Programming Voltage Control1 */
120: #define TS102_CARD_STS_VPP2_NC 0x00c0 /* NC */
121: #define TS102_CARD_STS_VPP2_VCC 0x0080 /* Vcc (3.3V or 5V) */
122: #define TS102_CARD_STS_VPP2_VPP 0x0040 /* Vpp (12V) */
123: #define TS102_CARD_STS_VPP2_0V 0x0000 /* 0V */
124: #define TS102_CARD_STS_WP 0x0100 /* Write Protect (1) */
125: #define TS102_CARD_STS_BVD_MASK 0x0600 /* Battery Voltage Detect */
126: #define TS102_CARD_STS_BVD_GOOD 0x0600 /* Battery good */
127: #define TS102_CARD_STS_BVD_LOW_OK 0x0400 /* Battery low, data OK */
128: #define TS102_CARD_STS_BVD_LOW_SUSPECT1 0x0200 /* Battery low, data suspect */
129: #define TS102_CARD_STS_BVD_LOW_SUSPECT0 0x0000 /* Battery low, data suspect */
130: #define TS102_CARD_STS_LVL 0x0800 /* Level (1) / Edge */
131: #define TS102_CARD_STS_RDY 0x1000 /* Ready (1) / Not Busy */
132: #define TS102_CARD_STS_VCCEN 0x2000 /* Powered Up (0) */
133: #define TS102_CARD_STS_RIEN 0x4000 /* Not Supported */
134: #define TS102_CARD_STS_ACEN 0x8000 /* Access Enabled (1) */
135:
136: /* TS102 Card Control Register definitions
137: */
138: #define TS102_CARD_CTL_AA_MASK 0x0003 /* Attribute Address A[25:24] */
139: #define TS102_CARD_CTL_IA_MASK 0x000c /* I/O Address A[25:24] */
140: #define TS102_CARD_CTL_IA_BITPOS 2 /* */
141: #define TS102_CARD_CTL_CES_MASK 0x0070 /* CE/address setup time */
142: #define TS102_CARD_CTL_CES_BITPOS 4 /* n+1 clocks */
143: #define TS102_CARD_CTL_OWE_MASK 0x0380 /* OE/WE width */
144: #define TS102_CARD_CTL_OWE_BITPOS 7 /* n+2 clocks */
145: #define TS102_CARD_CTL_CEH 0x0400 /* Chip enable hold time */
146: /* (0) - 1 clock */
147: /* (1) - 2 clocks */
148: #define TS102_CARD_CTL_SBLE 0x0800 /* SBus little endian */
149: #define TS102_CARD_CTL_PCMBE 0x1000 /* PCMCIA big endian */
150: #define TS102_CARD_CTL_RAHD 0x2000 /* Read ahead enable */
151: #define TS102_CARD_CTL_INCDIS 0x4000 /* Address increment disable */
152: #define TS102_CARD_CTL_PWRD 0x8000 /* Power down */
153:
154: /* Microcontroller Interrupt Register
155: */
156: #define TS102_UCTRL_INT_TXE_REQ 0x01 /* transmit FIFO empty */
157: #define TS102_UCTRL_INT_TXNF_REQ 0x02 /* transmit FIFO not full */
158: #define TS102_UCTRL_INT_RXNE_REQ 0x04 /* receive FIFO not empty */
159: #define TS102_UCTRL_INT_RXO_REQ 0x08 /* receive FIFO overflow */
160: #define TS102_UCTRL_INT_TXE_MSK 0x10 /* transmit FIFO empty */
161: #define TS102_UCTRL_INT_TXNF_MSK 0x20 /* transmit FIFO not full */
162: #define TS102_UCTRL_INT_RXNE_MSK 0x40 /* receive FIFO not empty */
163: #define TS102_UCTRL_INT_RXO_MSK 0x80 /* receive FIFO overflow */
164:
165: /* TS102 Microcontroller Data Register (only 8 bits are significant).
166: */
167: #define TS102_UCTRL_DATA_MASK 0xff
168:
169: /* TS102 Microcontroller Status Register.
170: * read 1 if asserted
171: * write 1 to clear
172: */
173: #define TS102_UCTRL_STS_TXE_STA 0x01 /* transmit FIFO empty */
174: #define TS102_UCTRL_STS_TXNF_STA 0x02 /* transmit FIFO not full */
175: #define TS102_UCTRL_STS_RXNE_STA 0x04 /* receive FIFO not empty */
176: #define TS102_UCTRL_STS_RXO_STA 0x08 /* receive FIFO overflow */
177: #define TS102_UCTRL_STS_MASK 0x0f /* Only 4 bits significant */
178:
179: enum ts102_opcode { /* Argument Returned */
180: TS102_OP_RD_SERIAL_NUM=0x01, /* none ack + 4 bytes */
181: TS102_OP_RD_ETHER_ADDR=0x02, /* none ack + 6 bytes */
182: TS102_OP_RD_HW_VERSION=0x03, /* none ack + 2 bytes */
183: TS102_OP_RD_UCTLR_VERSION=0x04, /* none ack + 2 bytes */
184: TS102_OP_RD_MAX_TEMP=0x05, /* none ack + 1 bytes */
185: TS102_OP_RD_MIN_TEMP=0x06, /* none ack + 1 bytes */
186: TS102_OP_RD_CURRENT_TEMP=0x07, /* none ack + 1 bytes */
187: TS102_OP_RD_SYSTEM_VARIANT=0x08, /* none ack + 4 bytes */
188: TS102_OP_RD_POWERON_CYCLES=0x09, /* none ack + 4 bytes */
189: TS102_OP_RD_POWERON_SECONDS=0x0a, /* none ack + 4 bytes */
190: TS102_OP_RD_RESET_STATUS=0x0b, /* none ack + 1 bytes */
191: #define TS102_RESET_STATUS_RESERVED0 0x00
192: #define TS102_RESET_STATUS_POWERON 0x01
193: #define TS102_RESET_STATUS_KEYBOARD 0x02
194: #define TS102_RESET_STATUS_WATCHDOG 0x03
195: #define TS102_RESET_STATUS_TIMEOUT 0x04
196: #define TS102_RESET_STATUS_SOFTWARE 0x05
197: #define TS102_RESET_STATUS_BROWNOUT 0x06
198: #define TS102_RESET_STATUS_RESERVED1 0x07
199: TS102_OP_RD_EVENT_STATUS=0x0c, /* none ack + 2 bytes */
200: #define TS102_EVENT_STATUS_SHUTDOWN_REQUEST 0x0001
201: #define TS102_EVENT_STATUS_LOW_POWER_WARNING 0x0002
202: /* Internal Warning Changed 0x0002 */
203: #define TS102_EVENT_STATUS_VERY_LOW_POWER_WARNING 0x0004
204: /* Discharge Event 0x0004 */
205: #define TS102_EVENT_STATUS_BATT_CHANGED 0x0008
206: /* Internal Status Changed 0x0008 */
207: #define TS102_EVENT_STATUS_EXT_KEYBOARD_STATUS_CHANGE 0x0010
208: #define TS102_EVENT_STATUS_EXT_MOUSE_STATUS_CHANGE 0x0020
209: #define TS102_EVENT_STATUS_EXTERNAL_VGA_STATUS_CHANGE 0x0040
210: #define TS102_EVENT_STATUS_LID_STATUS_CHANGE 0x0080
211: #define TS102_EVENT_STATUS_MICROCONTROLLER_ERROR 0x0100
212: #define TS102_EVENT_STATUS_RESERVED 0x0200
213: /* Wakeup 0x0200 */
214: #define TS102_EVENT_STATUS_EXT_BATT_STATUS_CHANGE 0x0400
215: #define TS102_EVENT_STATUS_EXT_BATT_CHARGING_STATUS_CHANGE 0x0800
216: #define TS102_EVENT_STATUS_EXT_BATT_LOW_POWER 0x1000
217: #define TS102_EVENT_STATUS_DC_STATUS_CHANGE 0x2000
218: #define TS102_EVENT_STATUS_CHARGING_STATUS_CHANGE 0x4000
219: #define TS102_EVENT_STATUS_POWERON_BTN_PRESSED 0x8000
220: TS102_OP_RD_REAL_TIME_CLK=0x0d, /* none ack + 7 bytes */
221: TS102_OP_RD_EXT_VGA_PORT=0x0e, /* none ack + 1 bytes */
222: TS102_OP_RD_UCTRL_ROM_CKSUM=0x0f, /* none ack + 2 bytes */
223: TS102_OP_RD_ERROR_STATUS=0x10, /* none ack + 2 bytes */
224: #define TS102_ERROR_STATUS_NO_ERROR 0x00
225: #define TS102_ERROR_STATUS_COMMAND_ERROR 0x01
226: #define TS102_ERROR_STATUS_EXECUTION_ERROR 0x02
227: #define TS102_ERROR_STATUS_PHYSICAL_ERROR 0x04
228: TS102_OP_RD_EXT_STATUS=0x11, /* none ack + 2 bytes */
229: #define TS102_EXT_STATUS_MAIN_POWER_AVAILABLE 0x0001
230: #define TS102_EXT_STATUS_INTERNAL_BATTERY_ATTACHED 0x0002
231: #define TS102_EXT_STATUS_EXTERNAL_BATTERY_ATTACHED 0x0004
232: #define TS102_EXT_STATUS_EXTERNAL_VGA_ATTACHED 0x0008
233: #define TS102_EXT_STATUS_EXTERNAL_KEYBOARD_ATTACHED 0x0010
234: #define TS102_EXT_STATUS_EXTERNAL_MOUSE_ATTACHED 0x0020
235: #define TS102_EXT_STATUS_LID_DOWN 0x0040
236: #define TS102_EXT_STATUS_INTERNAL_BATTERY_CHARGING 0x0080
237: #define TS102_EXT_STATUS_EXTERNAL_BATTERY_CHARGING 0x0100
238: #define TS102_EXT_STATUS_INTERNAL_BATTERY_DISCHARGING 0x0200
239: #define TS102_EXT_STATUS_EXTERNAL_BATTERY_DISCHARGING 0x0400
240: TS102_OP_RD_USER_CONFIG=0x12, /* none ack + 2 bytes */
241: TS102_OP_RD_UCTRL_VLT=0x13, /* none ack + 1 bytes */
242: TS102_OP_RD_INT_BATT_VLT=0x14, /* none ack + 1 bytes */
243: TS102_OP_RD_DC_IN_VLT=0x15, /* none ack + 1 bytes */
244: TS102_OP_RD_HORZ_PRT_VLT=0x16, /* none ack + 1 bytes */
245: TS102_OP_RD_VERT_PTR_VLT=0x17, /* none ack + 1 bytes */
246: TS102_OP_RD_INT_CHARGE_RATE=0x18, /* none ack + 1 bytes */
247: TS102_OP_RD_EXT_CHARGE_RATE=0x19, /* none ack + 1 bytes */
248: TS102_OP_RD_RTC_ALARM=0x1a, /* none ack + 7 bytes */
249: TS102_OP_RD_EVENT_STATUS_NO_RESET=0x1b, /* none ack + 2 bytes */
250: TS102_OP_RD_INT_KBD_LAYOUT=0x1c, /* none ack + 2 bytes */
251: TS102_OP_RD_EXT_KBD_LAYOUT=0x1d, /* none ack + 2 bytes */
252: TS102_OP_RD_EEPROM_STATUS=0x1e, /* none ack + 2 bytes */
253: #define TS102_EEPROM_STATUS_FACTORY_AREA_CHECKSUM_FAIL 0x01
254: #define TS102_EEPROM_STATUS_CONSUMER_AREA_CHECKSUM_FAIL 0x02
255: #define TS102_EEPROM_STATUS_USER_AREA_CHECKSUM_FAIL 0x04
256: #define TS102_EEPROM_STATUS_VPD_AREA_CHECKSUM_FAIL 0x08
257:
258: /* Read/Write/Modify Commands
259: */
260: TS102_OP_CTL_LCD=0x20, /* 4 byte mask ack + 4 bytes */
261: #define TS102_LCD_CAPS_LOCK 0x0001
262: #define TS102_LCD_SCROLL_LOCK 0x0002
263: #define TS102_LCD_NUMLOCK 0x0004
264: #define TS102_LCD_DISK_ACTIVE 0x0008
265: #define TS102_LCD_LAN_ACTIVE 0x0010
266: #define TS102_LCD_WAN_ACTIVE 0x0020
267: #define TS102_LCD_PCMCIA_ACTIVE 0x0040
268: #define TS102_LCD_DC_OK 0x0080
269: #define TS102_LCD_COMPOSE 0x0100
270: TS102_OP_CTL_BITPORT=0x21, /* mask ack + 1 byte */
271: #define TS102_BITPORT_TFTPWR 0x01 /* TFT power (low) */
272: #define TS102_BITPORT_SYNCINVA 0x02 /* ext. monitor sync (low) */
273: #define TS102_BITPORT_SYNCINVB 0x04 /* ext. monitor sync (low) */
274: #define TS102_BITPORT_BP_DIS 0x08 /* no bootprom from pcmcia (high) */
275: /* boot from pcmcia (low) */
276: #define TS102_BITPORT_ENCSYNC 0x10 /* enab composite sync (low) */
277: #define TS102_BITPORT_DISK_POWER 0x20 /* internal disk power (low) */
278: TS102_OP_CTL_DEV=0x22, /* mask ack + 1 byte */
279: #define TS102_DEVCTL_CHARGE_DISABLE 0x01 /* dis/en charging */
280: #define TS102_DEVCTL_POINTER_DISABLE 0x04 /* dis/en pointer */
281: #define TS102_DEVCTL_KEYCLICK 0x08 /* keyclick? */
282: #define TS102_DEVCTL_INT_BTNCLICK 0x10 /* internal button click? */
283: #define TS102_DEVCTL_EXT_BTNCLICK 0x20 /* ext. button click?? */
284: TS102_OP_CTL_SPEAKER_VOLUME=0x23, /* mask ack + 1 byte */
285: TS102_OP_CTL_TFT_BRIGHTNESS=0x24, /* mask ack + 1 byte */
286: TS102_OP_CTL_WATCHDOG=0x25, /* mask ack + 1 byte */
287: TS102_OP_CTL_FCTRY_EEPROM=0x26, /* mask ack + 1 byte */
288: TS102_OP_CTL_SECURITY_KEY=0x27, /* no idea */
289: TS102_OP_CTL_KDB_TIME_UNTL_RTP=0x28, /* mask ack + 1 byte */
290: TS102_OP_CTL_KBD_TIME_BTWN_RPTS=0x29, /* mask ack + 1 byte */
291: TS102_OP_CTL_TIMEZONE=0x2a, /* mask ack + 1 byte */
292: TS102_OP_CTL_MARK_SPACE_RATIO=0x2b, /* mask ack + 1 byte */
293: TS102_OP_CTL_MOUSE_SENS=0x2c, /* mask ack + 1 byte */
294: TS102_OP_CTL_MOUSE_SCAN=0x2d, /* no idea invalid?*/
295: TS102_OP_CTL_DIAGNOSTIC_MODE=0x2e, /* mask ack + 1 byte */
296: #define TS102_DIAGNOSTIC_MODE_CMD_DIAG_ON_LCD 0x01
297: #define TS102_DIAGNOSTIC_MODE_KDB_MS_9600 0x02
298: TS102_OP_CTL_SCREEN_CONTRAST=0x2f, /* mask ack + 1 byte */
299:
300: /* Commands returning no status
301: */
302: TS102_OP_CMD_RING_BELL=0x30, /* msb,lsb ack */
303: TS102_OP_RD_INPUT_SOURCE=0x31, /* no idea */
304: TS102_OP_CMD_DIAGNOSTIC_STATUS=0x32, /* msb,lsb ack */
305: TS102_OP_CMD_CLR_KEY_COMBO_TBL=0x33, /* none ack */
306: TS102_OP_CMD_SOFTWARE_RESET=0x34, /* none ack */
307: TS102_OP_CMD_SET_RTC=0x35, /* smhddmy ack */
308: TS102_OP_CMD_RECAL_PTR=0x36, /* none ack */
309: TS102_OP_CMD_SET_BELL_FREQ=0x37, /* msb,lsb ack */
310: TS102_OP_CMD_SET_INT_BATT_RATE=0x39, /* charge-lvl ack */
311: TS102_OP_CMD_SET_EXT_BATT_RATE=0x3a, /* charge-lvl ack */
312: TS102_OP_CMD_SET_RTC_ALARM=0x3b, /* smhddmy ack */
313:
314: /* Block transfer commands
315: */
316: TS102_OP_BLK_RD_EEPROM=0x40, /* len off ack <data> */
317: TS102_OP_BLK_WR_EEPROM=0x41, /* len off <data> ack */
318: TS102_OP_BLK_WR_STATUS=0x42, /* len off <data> ack */
319: TS102_OP_BLK_DEF_SPCL_CHAR=0x43, /* len off <8b data> ack */
320: #define TS102_BLK_OFF_DEF_WAN1 0
321: #define TS102_BLK_OFF_DEF_WAN2 1
322: #define TS102_BLK_OFF_DEF_LAN1 2
323: #define TS102_BLK_OFF_DEF_LAN2 3
324: #define TS102_BLK_OFF_DEF_PCMCIA 4
325: #define TS102_BLK_OFF_DEF_DC_GOOD 5
326: #define TS102_BLK_OFF_DEF_BACKSLASH 6
327:
328: /* Generic commands
329: */
330: TS102_OP_GEN_DEF_KEY_COMBO_ENT=0x50, /* seq com-length ack */
331: TS102_OP_GEN_DEF_STRING_TBL_ENT=0x51, /* str-code len <str> ack */
332: TS102_OP_GEN_DEF_STS_CTRN_DISP=0x52, /* len <msg> ack */
333:
334: /* Generic commands with optional status
335: */
336: TS102_OP_GEN_STS_EMU_COMMAND=0x64, /* <command> ack */
337: TS102_OP_GEN_STS_RD_EMU_REGISTER=0x65, /* reg ack + 1 byte */
338: TS102_OP_GEN_STS_WR_EMU_REGISTER=0x66, /* reg,val ack */
339: TS102_OP_GEN_STS_RD_EMU_RAM=0x67, /* addr ack + 1 byte */
340: TS102_OP_GEN_STS_WR_EMU_RAM=0x68, /* addr,val ack */
341: TS102_OP_GEN_STS_RD_BQ_REGISTER=0x69, /* reg ack + 1 byte */
342: TS102_OP_GEN_STS_WR_BQ_REGISTER=0x6a, /* reg,val ack */
343:
344: /* Administration commands
345: */
346: TS102_OP_ADMIN_SET_USER_PASS=0x70, /* len <pass> ack */
347: TS102_OP_ADMIN_VRFY_USER_PASS=0x71, /* len <pass> ack + status */
348: TS102_OP_ADMIN_GET_SYSTEM_PASS=0x72, /* none ack + <7bytekey> */
349: TS102_OP_ADMIN_VRFY_SYSTEM_PASS=0x73, /* len <pass> ack + status */
350: TS102_OP_RD_INT_CHARGE_LEVEL=0x7a, /* ack + 2 byte */
351: TS102_OP_RD_EXT_CHARGE_LEVEL=0x7b, /* ack + 2 byte */
352: #define TS102_CHARGE_UNKNOWN 0xfa
353: TS102_OP_SLEEP=0x80, /* supposedly sleeps, not sure */
354: TS102_OP_ADMIN_POWER_OFF=0x82, /* len <pass> none */
355: TS102_OP_ADMIN_POWER_RESTART=0x83, /* msb,xx,lsb none */
356: };
357:
358: #define TS102_UCTRL_ACK 0xfe
359: #define TS102_UCTRL_NACK 0xfc
360: #define TS102_UCTRL_INTR 0xfa
361:
362: #endif /* _SPARC_DEV_TS102REG_H */
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