Annotation of sys/arch/sparc/dev/spifreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: spifreg.h,v 1.10 2003/06/02 18:40:59 jason Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
! 5: * All rights reserved.
! 6: *
! 7: * Redistribution and use in source and binary forms, with or without
! 8: * modification, are permitted provided that the following conditions
! 9: * are met:
! 10: * 1. Redistributions of source code must retain the above copyright
! 11: * notice, this list of conditions and the following disclaimer.
! 12: * 2. Redistributions in binary form must reproduce the above copyright
! 13: * notice, this list of conditions and the following disclaimer in the
! 14: * documentation and/or other materials provided with the distribution.
! 15: *
! 16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 18: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
! 19: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
! 20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 22: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
! 24: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
! 25: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 26: * POSSIBILITY OF SUCH DAMAGE.
! 27: */
! 28:
! 29: struct ppcregs {
! 30: volatile u_int8_t in_pdata; /* input data reg */
! 31: volatile u_int8_t in_pstat; /* input status reg */
! 32: volatile u_int8_t in_pctrl; /* input control reg */
! 33: volatile u_int8_t in_pweird; /* input weird reg */
! 34: volatile u_int8_t out_pdata; /* output data reg */
! 35: volatile u_int8_t out_pstat; /* output status reg */
! 36: volatile u_int8_t out_pctrl; /* output control reg */
! 37: volatile u_int8_t out_pweird; /* output weird reg */
! 38: volatile u_int8_t _unused[500]; /* unused space */
! 39: volatile u_int8_t iack_pdata; /* intr-ack data reg */
! 40: volatile u_int8_t iack_pstat; /* intr-ack status reg */
! 41: volatile u_int8_t iack_pctrl; /* intr-ack control reg */
! 42: volatile u_int8_t iack_pweird; /* intr-ack weird reg */
! 43: };
! 44:
! 45: /* Parallel Status: read only */
! 46: #define PPC_PSTAT_ERROR 0x08 /* error */
! 47: #define PPC_PSTAT_SELECT 0x10 /* select */
! 48: #define PPC_PSTAT_PAPER 0x20 /* paper out */
! 49: #define PPC_PSTAT_ACK 0x40 /* ack */
! 50: #define PPC_PSTAT_BUSY 0x80 /* busy */
! 51:
! 52: /* Parallel Control: read/write */
! 53: #define PPC_CTRL_STROBE 0x01 /* strobe, 1=drop strobe */
! 54: #define PPC_CTRL_AFX 0x02 /* auto form-feed */
! 55: #define PPC_CTRL_INIT 0x04 /* init, 1=enable printer */
! 56: #define PPC_CTRL_SLCT 0x08 /* SLC, 1=select printer */
! 57: #define PPC_CTRL_IRQE 0x10 /* IRQ, 1=enable intrs */
! 58: #define PPC_CTRL_OUTPUT 0x20 /* direction: 1=ppc out */
! 59:
! 60: /*
! 61: * The 'stc' is a Cirrus Logic CL-CD180 (either revision B or revision C)
! 62: */
! 63: struct stcregs {
! 64: volatile u_int8_t _unused0[1]; /* 0x00 unused */
! 65: volatile u_int8_t ccr; /* channel command reg */
! 66: volatile u_int8_t srer; /* service req enable reg */
! 67: volatile u_int8_t cor1; /* channel option reg 1 */
! 68: volatile u_int8_t cor2; /* channel option reg 2 */
! 69: volatile u_int8_t cor3; /* channel option reg 3 */
! 70: volatile u_int8_t ccsr; /* channel cntrl status reg */
! 71: volatile u_int8_t rdcr; /* rx data count reg */
! 72: volatile u_int8_t _unused1[1]; /* 0x08 unused */
! 73: volatile u_int8_t schr1; /* special char reg 1 */
! 74: volatile u_int8_t schr2; /* special char reg 2 */
! 75: volatile u_int8_t schr3; /* special char reg 3 */
! 76: volatile u_int8_t schr4; /* special char reg 4 */
! 77: volatile u_int8_t _unused2[3]; /* 0x0d - 0x0f unused */
! 78:
! 79: volatile u_int8_t mcor1; /* modem change option reg 1 */
! 80: volatile u_int8_t mcor2; /* modem change option reg 2 */
! 81: volatile u_int8_t mcr; /* modem change reg */
! 82: volatile u_int8_t _unused3[5]; /* 0x13 - 0x17 unused */
! 83: volatile u_int8_t rtpr; /* rx timeout period reg */
! 84: volatile u_int8_t _unused4[7];
! 85:
! 86: volatile u_int8_t _unused5[8]; /* 0x19 - 0x27 unused */
! 87: volatile u_int8_t msvr; /* modem signal value reg */
! 88: volatile u_int8_t msvrts; /* modem sig value rts reg */
! 89: volatile u_int8_t msvdtr; /* modem sig value dtr reg */
! 90: volatile u_int8_t _unused6[5]; /* 0x2b - 0x2f unused */
! 91:
! 92: volatile u_int8_t _unused7[1]; /* 0x30 unused */
! 93: volatile u_int8_t rbprh; /* rx bit rate period reg hi */
! 94: volatile u_int8_t rbprl; /* rx bit rate period reg lo */
! 95: volatile u_int8_t rbr; /* rx bit reg */
! 96: volatile u_int8_t _unused8[5]; /* 0x34 - 0x38 unused */
! 97: volatile u_int8_t tbprh; /* tx bit rate period reg hi */
! 98: volatile u_int8_t tbprl; /* tx bit rate period reg lo */
! 99: volatile u_int8_t _unused9[5]; /* 0x34 - 0x38 unused */
! 100:
! 101: volatile u_int8_t gsvr; /* global service vector reg */
! 102: volatile u_int8_t gscr1; /* global service chan reg 1 */
! 103: volatile u_int8_t gscr2; /* global service chan reg 2 */
! 104: volatile u_int8_t gscr3; /* global service chan reg 3 */
! 105: volatile u_int8_t _unused10[12]; /* 0x44 - 0x4f unused */
! 106:
! 107: volatile u_int8_t _unused11[16]; /* 0x50 - 0x5f unused */
! 108:
! 109: volatile u_int8_t _unused12[1]; /* 0x60 unused */
! 110: volatile u_int8_t msmr; /* modem service match reg */
! 111: volatile u_int8_t tsmr; /* tx service match reg */
! 112: volatile u_int8_t rsmr; /* rx service match reg */
! 113: volatile u_int8_t car; /* channel access reg */
! 114: volatile u_int8_t srsr; /* service request stat reg */
! 115: volatile u_int8_t srcr; /* service request conf reg */
! 116: volatile u_int8_t _unused13[4]; /* 0x67 - 0x6a unused */
! 117: volatile u_int8_t gfrcr; /* global firmwr rev code reg */
! 118: volatile u_int8_t _unused14[4]; /* 0x6c - 0x6f unused */
! 119:
! 120: volatile u_int8_t pprh; /* prescalar period reg hi */
! 121: volatile u_int8_t pprl; /* prescalar period reg lo */
! 122: volatile u_int8_t _unused15[3]; /* 0x72 - 0x74 unused */
! 123: volatile u_int8_t mrar; /* modem request ack reg */
! 124: volatile u_int8_t trar; /* tx request ack reg */
! 125: volatile u_int8_t rrar; /* rx request ack reg */
! 126: volatile u_int8_t rdr; /* rx data reg */
! 127: volatile u_int8_t _unused16[1]; /* 0x79 unused */
! 128: volatile u_int8_t rcsr; /* rx char status reg */
! 129: volatile u_int8_t tdr; /* tx data reg */
! 130: volatile u_int8_t _unused17[3]; /* 0x7c - 0x7e unused */
! 131: volatile u_int8_t eosrr; /* end of service req reg */
! 132: };
! 133:
! 134: /* Global Firmware Revision Code Register (rw) */
! 135: #define CD180_GFRCR_REV_B 0x81 /* CL-CD180B */
! 136: #define CD180_GFRCR_REV_C 0x82 /* CL-CD180C */
! 137:
! 138: /* Service Request Configuration Register (rw) (CD180C or higher) */
! 139: #define CD180_SRCR_PKGTYP 0x80 /* pkg type,0=PLCC,1=PQFP */
! 140: #define CD180_SRCR_REGACKEN 0x40 /* register ack enable */
! 141: #define CD180_SRCR_DAISYEN 0x20 /* daisy chain enable */
! 142: #define CD180_SRCR_GLOBPRI 0x10 /* global priority */
! 143: #define CD180_SRCR_UNFAIR 0x08 /* use unfair interrupts */
! 144: #define CD180_SRCR_AUTOPRI 0x02 /* automatic priority */
! 145: #define CD180_SRCR_PRISEL 0x01 /* select rx/tx as high pri */
! 146:
! 147: /* Prescalar Period Register High (rw) */
! 148: #define CD180_PPRH 0xf0 /* high byte */
! 149: #define CD180_PPRL 0x00 /* low byte */
! 150:
! 151: /* Global Service Vector Register (rw) */
! 152: /* Modem Request Acknowledgement Register (ro) (and IACK equivalent) */
! 153: /* Receive Request Acknowledgement Register (ro) (and IACK equivalent) */
! 154: /* Transmit Request Acknowledgement Register (ro) (and IACK equivalent) */
! 155: #define CD180_GSVR_USERMASK 0xf8 /* user defined bits */
! 156: #define CD180_GSVR_IMASK 0x07 /* interrupt type mask */
! 157: #define CD180_GSVR_NOREQUEST 0x00 /* no request pending */
! 158: #define CD180_GSVR_STATCHG 0x01 /* modem signal change */
! 159: #define CD180_GSVR_TXDATA 0x02 /* tx service request */
! 160: #define CD180_GSVR_RXGOOD 0x03 /* rx service request */
! 161: #define CD180_GSVR_reserved1 0x04 /* reserved */
! 162: #define CD180_GSVR_reserved2 0x05 /* reserved */
! 163: #define CD180_GSVR_reserved3 0x06 /* reserved */
! 164: #define CD180_GSVR_RXEXCEPTION 0x07 /* rx exception request */
! 165:
! 166: /* Service Request Status Register (ro) (CD180C and higher) */
! 167: #define CD180_SRSR_MREQINT 0x01 /* modem request internal */
! 168: #define CD180_SRSR_MREQEXT 0x02 /* modem request external */
! 169: #define CD180_SRSR_TREQINT 0x04 /* tx request internal */
! 170: #define CD180_SRSR_TREQEXT 0x08 /* tx request external */
! 171: #define CD180_SRSR_RREQINT 0x10 /* rx request internal */
! 172: #define CD180_SRSR_RREQEXT 0x20 /* rx request external */
! 173: #define CD180_SRSR_ILV_MASK 0xc0 /* internal service context */
! 174: #define CD180_SRSR_ILV_NONE 0x00 /* not in service context */
! 175: #define CD180_SRSR_ILV_RX 0xc0 /* in rx service context */
! 176: #define CD180_SRSR_ILV_TX 0x80 /* in tx service context */
! 177: #define CD180_SRSR_ILV_MODEM 0x40 /* in modem service context */
! 178:
! 179: /* Global Service Channel Register 1,2,3 (rw) */
! 180: #define CD180_GSCR_CHANNEL(gscr) (((gscr) >> 2) & 7)
! 181:
! 182: /* Receive Data Count Register (ro) */
! 183: #define CD180_RDCR_MASK 0x0f /* mask for fifo length */
! 184:
! 185: /* Receive Character Status Register (ro) */
! 186: #define CD180_RCSR_TO 0x80 /* time out */
! 187: #define CD180_RCSR_SCD2 0x40 /* special char detect 2 */
! 188: #define CD180_RCSR_SCD1 0x20 /* special char detect 1 */
! 189: #define CD180_RCSR_SCD0 0x10 /* special char detect 0 */
! 190: #define CD180_RCSR_BE 0x08 /* break exception */
! 191: #define CD180_RCSR_PE 0x04 /* parity exception */
! 192: #define CD180_RCSR_FE 0x02 /* framing exception */
! 193: #define CD180_RCSR_OE 0x01 /* overrun exception */
! 194:
! 195: /* Service Request Enable Register (rw) */
! 196: #define CD180_SRER_DSR 0x80 /* DSR service request */
! 197: #define CD180_SRER_CD 0x40 /* CD service request */
! 198: #define CD180_SRER_CTS 0x20 /* CTS service request */
! 199: #define CD180_SRER_RXD 0x10 /* RXD service request */
! 200: #define CD180_SRER_RXSCD 0x08 /* RX special char request */
! 201: #define CD180_SRER_TXD 0x04 /* TX ready service request */
! 202: #define CD180_SRER_TXE 0x02 /* TX empty service request */
! 203: #define CD180_SRER_NNDT 0x01 /* No new data timeout req */
! 204:
! 205: /* Channel Command Register (rw) */
! 206: /* Reset Channel Command */
! 207: #define CD180_CCR_CMD_RESET 0x80 /* chip/channel reset */
! 208: #define CD180_CCR_RESETALL 0x01 /* global reset */
! 209: #define CD180_CCR_RESETCHAN 0x00 /* current channel reset */
! 210: /* Channel Option Register Command */
! 211: #define CD180_CCR_CMD_COR 0x40 /* channel opt reg changed */
! 212: #define CD180_CCR_CORCHG1 0x02 /* cor1 has changed */
! 213: #define CD180_CCR_CORCHG2 0x04 /* cor2 has changed */
! 214: #define CD180_CCR_CORCHG3 0x08 /* cor3 has changed */
! 215: /* Send Special Character Command */
! 216: #define CD180_CCR_CMD_SPC 0x20 /* send special chars changed */
! 217: #define CD180_CCR_SSPC0 0x01 /* send special char 0 change */
! 218: #define CD180_CCR_SSPC1 0x02 /* send special char 1 change */
! 219: #define CD180_CCR_SSPC2 0x04 /* send special char 2 change */
! 220: /* Channel Control Command */
! 221: #define CD180_CCR_CMD_CHAN 0x10 /* channel control command */
! 222: #define CD180_CCR_CHAN_TXEN 0x08 /* enable channel tx */
! 223: #define CD180_CCR_CHAN_TXDIS 0x04 /* disable channel tx */
! 224: #define CD180_CCR_CHAN_RXEN 0x02 /* enable channel rx */
! 225: #define CD180_CCR_CHAN_RXDIS 0x01 /* disable channel rx */
! 226:
! 227: /* Channel Option Register 1 (rw) */
! 228: #define CD180_COR1_EVENPAR 0x00 /* even parity */
! 229: #define CD180_COR1_ODDPAR 0x80 /* odd parity */
! 230: #define CD180_COR1_PARMODE_NO 0x00 /* no parity */
! 231: #define CD180_COR1_PARMODE_FORCE 0x20 /* force (odd=1, even=0) */
! 232: #define CD180_COR1_PARMODE_NORMAL 0x40 /* normal parity mode */
! 233: #define CD180_COR1_PARMODE_NA 0x60 /* notused */
! 234: #define CD180_COR1_IGNPAR 0x10 /* ignore parity */
! 235: #define CD180_COR1_STOP1 0x00 /* 1 stop bit */
! 236: #define CD180_COR1_STOP15 0x04 /* 1.5 stop bits */
! 237: #define CD180_COR1_STOP2 0x08 /* 2 stop bits */
! 238: #define CD180_COR1_STOP25 0x0c /* 2.5 stop bits */
! 239: #define CD180_COR1_CS5 0x00 /* 5 bit characters */
! 240: #define CD180_COR1_CS6 0x01 /* 6 bit characters */
! 241: #define CD180_COR1_CS7 0x02 /* 7 bit characters */
! 242: #define CD180_COR1_CS8 0x03 /* 8 bit characters */
! 243:
! 244: /* Channel Option Register 2 (rw) */
! 245: #define CD180_COR2_IXM 0x80 /* implied xon mode */
! 246: #define CD180_COR2_TXIBE 0x40 /* tx in-band flow control */
! 247: #define CD180_COR2_ETC 0x20 /* embedded tx command enbl */
! 248: #define CD180_COR2_LLM 0x10 /* local loopback mode */
! 249: #define CD180_COR2_RLM 0x08 /* remote loopback mode */
! 250: #define CD180_COR2_RTSAO 0x04 /* RTS automatic output enbl */
! 251: #define CD180_COR2_CTSAE 0x02 /* CTS automatic enable */
! 252: #define CD180_COR2_DSRAE 0x01 /* DSR automatic enable */
! 253:
! 254: /* Channel Option Register 3 (rw) */
! 255: #define CD180_COR3_XON2 0x80 /* XON char in spc1&3 */
! 256: #define CD180_COR3_XON1 0x00 /* XON char in spc1 */
! 257: #define CD180_COR3_XOFF2 0x40 /* XOFF char in spc2&4 */
! 258: #define CD180_COR3_XOFF1 0x00 /* XOFF char in spc2 */
! 259: #define CD180_COR3_FCT 0x20 /* flow control transparency */
! 260: #define CD180_COR3_SCDE 0x10 /* special char recognition */
! 261: #define CD180_COR3_RXFIFO_MASK 0x0f /* rx fifo threshold */
! 262:
! 263: /* Channel Control Status Register (ro) */
! 264: #define CD180_CCSR_RXEN 0x80 /* rx is enabled */
! 265: #define CD180_CCSR_RXFLOFF 0x40 /* rx flow-off */
! 266: #define CD180_CCSR_RXFLON 0x20 /* rx flow-on */
! 267: #define CD180_CCSR_TXEN 0x08 /* tx is enabled */
! 268: #define CD180_CCSR_TXFLOFF 0x04 /* tx flow-off */
! 269: #define CD180_CCSR_TXFLON 0x02 /* tx flow-on */
! 270:
! 271: /* Receiver Bit Register (ro) */
! 272: #define CD180_RBR_RXD 0x40 /* state of RxD pin */
! 273: #define CD180_RBR_STARTHUNT 0x20 /* looking for start bit */
! 274:
! 275: /* Modem Change Register (rw) */
! 276: #define CD180_MCR_DSR 0x80 /* DSR changed */
! 277: #define CD180_MCR_CD 0x40 /* CD changed */
! 278: #define CD180_MCR_CTS 0x20 /* CTS changed */
! 279:
! 280: /* Modem Change Option Register 1 (rw) */
! 281: #define CD180_MCOR1_DSRZD 0x80 /* catch 0->1 DSR changes */
! 282: #define CD180_MCOR1_CDZD 0x40 /* catch 0->1 CD changes */
! 283: #define CD180_MCOR1_CTSZD 0x40 /* catch 0->1 CTS changes */
! 284: #define CD180_MCOR1_DTRTHRESH 0x0f /* DTR threshold mask */
! 285:
! 286: /* Modem Change Option Register 2 (rw) */
! 287: #define CD180_MCOR2_DSROD 0x80 /* catch 1->0 DSR changes */
! 288: #define CD180_MCOR2_CDOD 0x40 /* catch 1->0 CD changes */
! 289: #define CD180_MCOR2_CTSOD 0x20 /* catch 1->0 CTS changes */
! 290:
! 291: /* Modem Signal Value Register (rw) */
! 292: #define CD180_MSVR_DSR 0x80 /* DSR input state */
! 293: #define CD180_MSVR_CD 0x40 /* CD input state */
! 294: #define CD180_MSVR_CTS 0x20 /* CTS input state */
! 295: #define CD180_MSVR_DTR 0x02 /* DTR output state */
! 296: #define CD180_MSVR_RTS 0x01 /* RTS output state */
! 297:
! 298: /* Modem Signal Value Register - Request To Send (w) (CD180C and higher) */
! 299: #define CD180_MSVRTS_RTS 0x01 /* RTS signal value */
! 300:
! 301: /* Modem Signal Value Register - Data Terminal Ready (w) (CD180C and higher) */
! 302: #define CD180_MSVDTR_DTR 0x02 /* DTR signal value */
! 303:
! 304: /*
! 305: * The register map for the SUNW,spif looks something like:
! 306: * Offset: Function:
! 307: * 0000 - 03ff Boot ROM
! 308: * 0400 - 0407 dtr latches (one per port)
! 309: * 0408 - 07ff unused
! 310: * 0800 - 087f CD180 registers (normal mapping)
! 311: * 0880 - 0bff unused
! 312: * 0c00 - 0c7f CD180 registers (*iack mapping)
! 313: * 0c80 - 0dff unused
! 314: * 0e00 - 1fff PPC registers
! 315: *
! 316: * One note about the DTR latches: The values stored there are reversed.
! 317: * By writing a 1 to the latch, DTR is lowered, and by writing a 0, DTR
! 318: * is raised. The latches cannot be read, and no other value can be written
! 319: * there or the system will crash due to "excessive bus loading (see
! 320: * SBus loading and capacitance spec)"
! 321: *
! 322: * The *iack registers are read/written with the IACK bit set. When
! 323: * the interrupt routine starts, it reads the MRAR, TRAR, and RRAR registers
! 324: * from this mapping. This signals an interrupt acknowledgement cycle.
! 325: * (NOTE: these are not really the MRAR, TRAR, and RRAR... They are copies
! 326: * of the GSVR, I just mapped them to the same location as the mrar, trar,
! 327: * and rrar because it seemed appropriate).
! 328: */
! 329: struct spifregs {
! 330: volatile u_int8_t _unused1[1024]; /* 0x000-0x3ff unused */
! 331: volatile u_int8_t dtrlatch[8]; /* per port dtr latch */
! 332: volatile u_int8_t _unused2[1016]; /* 0x408-0x7ff unused */
! 333: struct stcregs stc; /* regular cd-180 regs */
! 334: volatile u_int8_t _unused3[896]; /* 0x880-0xbff unused */
! 335: struct stcregs istc; /* *iack cd-180 regs */
! 336: volatile u_int8_t _unused4[384]; /* 0xc80-0xdff unused */
! 337: struct ppcregs ppc; /* parallel port regs */
! 338: };
! 339:
! 340: /*
! 341: * The mapping of minor device number -> card and port is done as
! 342: * follows by default:
! 343: *
! 344: * +---+---+---+---+---+---+---+---+
! 345: * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
! 346: * +---+---+---+---+---+---+---+---+
! 347: * | | | | | | | |
! 348: * | | | | | +---+---+---> port number
! 349: * | | | | |
! 350: * | | | | +---------------> unused
! 351: * | | | |
! 352: * | | | +-------------------> dialout (on tty ports)
! 353: * | | |
! 354: * | | +-----------------------> unused
! 355: * | |
! 356: * +---+---------------------------> card number
! 357: *
! 358: */
! 359: #define SPIF_MAX_CARDS 4
! 360: #define SPIF_MAX_TTY 8
! 361: #define SPIF_MAX_BPP 1
! 362:
! 363: /*
! 364: * device selectors
! 365: */
! 366: #define SPIF_CARD(x) ((minor(x) >> 6) & 0x03)
! 367: #define SPIF_PORT(x) (minor(x) & 0x07)
! 368: #define STTY_DIALOUT(x) (minor(x) & 0x10)
! 369:
! 370: #define STTY_RX_FIFO_THRESHOLD 4
! 371: #define STTY_RX_DTR_THRESHOLD 7
! 372: #define CD180_TX_FIFO_SIZE 8 /* 8 chars of fifo */
! 373:
! 374: /*
! 375: * These are the offsets of the MRAR, TRAR, and RRAR in *IACK space.
! 376: * The high bit must be set as per specs for the MSMR, TSMR, and RSMR.
! 377: */
! 378: #define SPIF_MSMR 0xf5 /* offset of MRAR | 0x80 */
! 379: #define SPIF_TSMR 0xf6 /* offset of TRAR | 0x80 */
! 380: #define SPIF_RSMR 0xf7 /* offset of RRAR | 0x80 */
! 381:
! 382: /*
! 383: * "verosc" node tells which oscillator we have.
! 384: */
! 385: #define SPIF_OSC9 1 /* 9.8304 MHz */
! 386: #define SPIF_OSC10 2 /* 10MHz */
! 387:
! 388: /*
! 389: * There are two interrupts, serial gets interrupt[0], and parallel
! 390: * gets interrupt[1]
! 391: */
! 392: #define SERIAL_INTR 0
! 393: #define PARALLEL_INTR 1
! 394:
! 395: /*
! 396: * spif tty flags
! 397: */
! 398: #define STTYF_CDCHG 0x01 /* carrier changed */
! 399: #define STTYF_RING_OVERFLOW 0x02 /* ring buffer overflowed */
! 400: #define STTYF_DONE 0x04 /* done... flush buffers */
! 401: #define STTYF_SET_BREAK 0x08 /* set break signal */
! 402: #define STTYF_CLR_BREAK 0x10 /* clear break signal */
! 403: #define STTYF_STOP 0x20 /* stopped */
! 404:
! 405: #define STTY_RBUF_SIZE (2 * 512)
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