Return to sireg.h CVS log

Up to [local] / sys / arch / sparc / dev

Annotation of sys/arch/sparc/dev/sireg.h, Revision 1.1.1.1

1.1       nbrk        1: /*     $OpenBSD: sireg.h,v 1.3 1997/08/08 08:25:30 downsj Exp $        */
                      2: /*     $NetBSD: sireg.h,v 1.3 1996/01/01 22:40:58 thorpej Exp $        */
                      3:
                      4: /*
                      5:  * Register map for the Sun3 SCSI Interface (si)
                      6:  * The first part of this register map is an NCR5380
                      7:  * SCSI Bus Interface Controller (SBIC).  The rest is a
                      8:  * DMA controller and custom logic in one of two flavors,
                      9:  * one for the OBIO interface (3/50,3/60) and one for the
                     10:  * VME interface (3/160,3/260,etc.), where some registers
                     11:  * are implemented only on one or the other, some on both.
                     12:  *
                     13:  * Modified for Sun 4 systems by Jason R. Thorpe <thorpej@NetBSD.ORG>.
                     14:  */
                     15:
                     16: /*
                     17:  * Note that the obio version on the 4/1xx (the so-called "SCSI Weird", or
                     18:  * "sw" controller) is laid out a bit differently, and hence the evilness
                     19:  * with unions.  Also, the "sw" doesn't appear to have a FIFO.
                     20:  */
                     21:
                     22: /*
                     23:  * Am5380 Register map (no padding)
                     24:  */
                     25: struct ncr5380regs {
                     26:        volatile u_char sci_r0;
                     27:        volatile u_char sci_r1;
                     28:        volatile u_char sci_r2;
                     29:        volatile u_char sci_r3;
                     30:        volatile u_char sci_r4;
                     31:        volatile u_char sci_r5;
                     32:        volatile u_char sci_r6;
                     33:        volatile u_char sci_r7;
                     34: };
                     35:
                     36: struct si_regs {
                     37:        struct ncr5380regs sci;
                     38:
                     39:        /* DMA controller registers */
                     40:        union {
                     41:                struct {
                     42:                        u_short _Dma_addrh;     /* dma address (VME only) */
                     43:                        u_short _Dma_addrl;     /* (high word, low word)  */
                     44:                } _si_u1_s;
                     45:                u_int           _Dma_addr;      /* dma address (OBIO) */
                     46:        } _si_u1;
                     47: #define dma_addrh      _si_u1._si_u1_s._Dma_addrh
                     48: #define dma_addrl      _si_u1._si_u1_s._Dma_addrl
                     49: #define dma_addr       _si_u1._Dma_addr
                     50:
                     51:        union {
                     52:                struct {
                     53:                        u_short _Dma_counth;    /* dma count   (VME only) */
                     54:                        u_short _Dma_countl;    /* (high word, low word)  */
                     55:                } _si_u2_s;
                     56:                u_int           _Dma_count;     /* dma count (OBIO) */
                     57:        } _si_u2;
                     58: #define dma_counth     _si_u2._si_u2_s._Dma_counth
                     59: #define dma_countl     _si_u2._si_u2_s._Dma_countl
                     60: #define dma_count      _si_u2._Dma_count
                     61:
                     62:        u_int           si_pad0;                /* no-existent register */
                     63:
                     64:        union {
                     65:                struct {
                     66:                        u_short _Fifo_data;     /* fifo data register */
                     67:                        u_short _Fifo_count;    /* fifo count register */
                     68:                } _si_u4_s;
                     69:                u_int           _Sw_csr;        /* sw control/status */
                     70:        } _si_u4;
                     71: #define fifo_data      _si_u4._si_u4_s._Fifo_data
                     72: #define fifo_count     _si_u4._si_u4_s._Fifo_count
                     73: #define sw_csr         _si_u4._Sw_csr
                     74:
                     75:        union {
                     76:                struct {
                     77:                        u_short _Si_csr;        /* si control/status */
                     78:                        u_short _Bprh;          /* VME byte pack high */
                     79:                } _si_u5_s;
                     80:                u_int   _Bpr;                   /* sw byte pack */
                     81:        } _si_u5;
                     82: #define si_csr         _si_u5._si_u5_s._Si_csr
                     83: #define si_bprh                _si_u5._si_u5_s._Bprh
                     84: #define sw_bpr         _si_u5._Bpr
                     85:
                     86:        /* The rest of these are on the VME interface only: */
                     87:        u_short                 si_bprl;        /* VME byte pack low */
                     88:        u_short                 si_iv_am;       /* bits 0-7: intr vector */
                     89:                                /* bits 8-13: addr modifier (VME only) */
                     90:                                                /* bits 14-15: unused */
                     91:        u_short                 fifo_cnt_hi;    /* high part of fifo_count (VME only) */
                     92:
                     93:        /* Whole thing repeats after 32 bytes. */
                     94:        u_short                 _space[3];
                     95: };
                     96:
                     97: /* possible values for the address modifier, vme version only */
                     98: #define VME_SUPV_DATA_24       0x3d00
                     99:
                    100: /*
                    101:  * Status Register.
                    102:  * Note:
                    103:  *     (r)     indicates bit is read only.
                    104:  *     (rw)    indicates bit is read or write.
                    105:  *     (v)     vme host adaptor interface only.
                    106:  *     (o)     sun3/50 onboard host adaptor interface only.
                    107:  *     (b)     both vme and sun3/50 host adaptor interfaces.
                    108:  */
                    109: #define SI_CSR_DMA_ACTIVE      0x8000  /* (r,o) dma transfer active */
                    110: #define SI_CSR_DMA_CONFLICT    0x4000  /* (r,b) reg accessed while dmaing */
                    111: #define SI_CSR_DMA_BUS_ERR     0x2000  /* (r,b) bus error during dma */
                    112: #define SI_CSR_ID              0x1000  /* (r,b) 0 for 3/50, 1 for SCSI-3, */
                    113:                                        /* 0 if SCSI-3 unmodified */
                    114: #define SI_CSR_FIFO_FULL       0x0800  /* (r,b) fifo full */
                    115: #define SI_CSR_FIFO_EMPTY      0x0400  /* (r,b) fifo empty */
                    116: #define SI_CSR_SBC_IP          0x0200  /* (r,b) sbc interrupt pending */
                    117: #define SI_CSR_DMA_IP          0x0100  /* (r,b) dma interrupt pending */
                    118: #define SI_CSR_LOB             0x00c0  /* (r,v) number of leftover bytes */
                    119: #define SI_CSR_LOB_THREE       0x00c0  /* (r,v) three leftover bytes */
                    120: #define SI_CSR_LOB_TWO         0x0080  /* (r,v) two leftover bytes */
                    121: #define SI_CSR_LOB_ONE         0x0040  /* (r,v) one leftover byte */
                    122: #define SI_CSR_BPCON           0x0020  /* (rw,v) byte packing control */
                    123:                                        /* dma is in 0=longwords, 1=words */
                    124: #define SI_CSR_DMA_EN          0x0010  /* (rw,v) dma/interrupt enable */
                    125: #define SI_CSR_SEND            0x0008  /* (rw,b) dma dir, 1=to device */
                    126: #define SI_CSR_INTR_EN         0x0004  /* (rw,b) interrupts enable */
                    127: #define SI_CSR_FIFO_RES                0x0002  /* (rw,b) inits fifo, 0=reset */
                    128: #define SI_CSR_SCSI_RES                0x0001  /* (rw,b) reset sbc and udc, 0=reset */