Annotation of sys/arch/sparc/dev/qereg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: qereg.h,v 1.7 2003/06/02 18:40:59 jason Exp $ */
2:
3: /*
4: * Copyright (c) 1998, 2000 Jason L. Wright.
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19: * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
20: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26: */
27:
28: /*
29: * Documentation for MACE chip can be found on AMD's website:
30: * http://www.amd.com/products/npd/techdocs/techdocs.html
31: */
32:
33: /*
34: * QE Channel registers
35: */
36: struct qe_cregs {
37: volatile u_int32_t ctrl; /* control */
38: volatile u_int32_t stat; /* status */
39: volatile u_int32_t rxds; /* rx descriptor ring ptr */
40: volatile u_int32_t txds; /* tx descriptor ring ptr */
41: volatile u_int32_t rimask; /* rx interrupt mask */
42: volatile u_int32_t timask; /* tx interrupt mask */
43: volatile u_int32_t qmask; /* qec error interrupt mask */
44: volatile u_int32_t mmask; /* mace error interrupt mask */
45: volatile u_int32_t rxwbufptr; /* local memory rx write ptr */
46: volatile u_int32_t rxrbufptr; /* local memory rx read ptr */
47: volatile u_int32_t txwbufptr; /* local memory tx write ptr */
48: volatile u_int32_t txrbufptr; /* local memory tx read ptr */
49: volatile u_int32_t ccnt; /* collision counter */
50: volatile u_int32_t pipg; /* inter-frame gap */
51: };
52:
53: /* qe_cregs.ctrl: control. */
54: #define QE_CR_CTRL_RXOFF 0x00000004 /* disable receiver */
55: #define QE_CR_CTRL_RESET 0x00000002 /* reset this channel */
56: #define QE_CR_CTRL_TWAKEUP 0x00000001 /* tx dma wakeup */
57:
58: /* qe_cregs.stat: status. */
59: #define QE_CR_STAT_EDEFER 0x10000000 /* excessive defers */
60: #define QE_CR_STAT_CLOSS 0x08000000 /* loss of carrier */
61: #define QE_CR_STAT_ERETRIES 0x04000000 /* >16 retries */
62: #define QE_CR_STAT_LCOLL 0x02000000 /* late tx collision */
63: #define QE_CR_STAT_FUFLOW 0x01000000 /* fifo underflow */
64: #define QE_CR_STAT_JERROR 0x00800000 /* jabber error */
65: #define QE_CR_STAT_BERROR 0x00400000 /* babble error */
66: #define QE_CR_STAT_TXIRQ 0x00200000 /* tx interrupt */
67: #define QE_CR_STAT_TCCOFLOW 0x00100000 /* tx collision cntr expired */
68: #define QE_CR_STAT_TXDERROR 0x00080000 /* tx descriptor is bad */
69: #define QE_CR_STAT_TXLERR 0x00040000 /* tx late error */
70: #define QE_CR_STAT_TXPERR 0x00020000 /* tx parity error */
71: #define QE_CR_STAT_TXSERR 0x00010000 /* tx sbus error ack */
72: #define QE_CR_STAT_RCCOFLOW 0x00001000 /* rx collision cntr expired */
73: #define QE_CR_STAT_RUOFLOW 0x00000800 /* rx runt counter expired */
74: #define QE_CR_STAT_MCOFLOW 0x00000400 /* rx missed counter expired */
75: #define QE_CR_STAT_RXFOFLOW 0x00000200 /* rx fifo over flow */
76: #define QE_CR_STAT_RLCOLL 0x00000100 /* rx late collision */
77: #define QE_CR_STAT_FCOFLOW 0x00000080 /* rx frame counter expired */
78: #define QE_CR_STAT_CECOFLOW 0x00000040 /* rx crc error cntr expired */
79: #define QE_CR_STAT_RXIRQ 0x00000020 /* rx interrupt */
80: #define QE_CR_STAT_RXDROP 0x00000010 /* rx dropped packet */
81: #define QE_CR_STAT_RXSMALL 0x00000008 /* rx buffer too small */
82: #define QE_CR_STAT_RXLERR 0x00000004 /* rx late error */
83: #define QE_CR_STAT_RXPERR 0x00000002 /* rx parity error */
84: #define QE_CR_STAT_RXSERR 0x00000001 /* rx sbus error ack */
85:
86: /*
87: * Errors: all status bits except for TX/RX IRQ
88: */
89: #define QE_CR_STAT_ALLERRORS \
90: ( QE_CR_STAT_EDEFER | QE_CR_STAT_CLOSS | QE_CR_STAT_ERETRIES \
91: | QE_CR_STAT_LCOLL | QE_CR_STAT_FUFLOW | QE_CR_STAT_JERROR \
92: | QE_CR_STAT_BERROR | QE_CR_STAT_TCCOFLOW | QE_CR_STAT_TXDERROR \
93: | QE_CR_STAT_TXLERR | QE_CR_STAT_TXPERR | QE_CR_STAT_TXSERR \
94: | QE_CR_STAT_RCCOFLOW | QE_CR_STAT_RUOFLOW | QE_CR_STAT_MCOFLOW \
95: | QE_CR_STAT_RXFOFLOW | QE_CR_STAT_RLCOLL | QE_CR_STAT_FCOFLOW \
96: | QE_CR_STAT_CECOFLOW | QE_CR_STAT_RXDROP | QE_CR_STAT_RXSMALL \
97: | QE_CR_STAT_RXLERR | QE_CR_STAT_RXPERR | QE_CR_STAT_RXSERR)
98:
99: /* qe_cregs.qmask: qec error interrupt mask. */
100: #define QE_CR_QMASK_COFLOW 0x00100000 /* collision cntr overflow */
101: #define QE_CR_QMASK_TXDERROR 0x00080000 /* tx descriptor error */
102: #define QE_CR_QMASK_TXLERR 0x00040000 /* tx late error */
103: #define QE_CR_QMASK_TXPERR 0x00020000 /* tx parity error */
104: #define QE_CR_QMASK_TXSERR 0x00010000 /* tx sbus error ack */
105: #define QE_CR_QMASK_RXDROP 0x00000010 /* rx packet dropped */
106: #define QE_CR_QMASK_RXSMALL 0x00000008 /* rx buffer too small */
107: #define QE_CR_QMASK_RXLERR 0x00000004 /* rx late error */
108: #define QE_CR_QMASK_RXPERR 0x00000002 /* rx parity error */
109: #define QE_CR_QMASK_RXSERR 0x00000001 /* rx sbus error ack */
110:
111: /* qe_cregs.mmask: MACE error interrupt mask. */
112: #define QE_CR_MMASK_EDEFER 0x10000000 /* excess defer */
113: #define QE_CR_MMASK_CLOSS 0x08000000 /* carrier loss */
114: #define QE_CR_MMASK_ERETRY 0x04000000 /* excess retry */
115: #define QE_CR_MMASK_LCOLL 0x02000000 /* late collision error */
116: #define QE_CR_MMASK_UFLOW 0x01000000 /* underflow */
117: #define QE_CR_MMASK_JABBER 0x00800000 /* jabber error */
118: #define QE_CR_MMASK_BABBLE 0x00400000 /* babble error */
119: #define QE_CR_MMASK_OFLOW 0x00000800 /* overflow */
120: #define QE_CR_MMASK_RXCOLL 0x00000400 /* rx coll-cntr overflow */
121: #define QE_CR_MMASK_RPKT 0x00000200 /* runt pkt overflow */
122: #define QE_CR_MMASK_MPKT 0x00000100 /* missed pkt overflow */
123:
124: /* qe_cregs.pipg: inter-frame gap. */
125: #define QE_CR_PIPG_TENAB 0x00000020 /* enable throttle */
126: #define QE_CR_PIPG_MMODE 0x00000010 /* manual mode */
127: #define QE_CR_PIPG_WMASK 0x0000000f /* sbus wait mask */
128:
129: /* MACE registers */
130: struct qe_mregs {
131: volatile u_int8_t rcvfifo; /*0*/ /* receive fifo */
132: volatile u_int8_t xmtfifo; /*1*/ /* transmit fifo */
133: volatile u_int8_t xmtfc; /*2*/ /* transmit frame control */
134: volatile u_int8_t xmtfs; /*3*/ /* transmit frame status */
135: volatile u_int8_t xmtrc; /*4*/ /* tx retry count */
136: volatile u_int8_t rcvfc; /*5*/ /* receive frame control */
137: volatile u_int8_t rcvfs; /*6*/ /* receive frame status */
138: volatile u_int8_t fifofc; /*7*/ /* fifo frame count */
139: volatile u_int8_t ir; /*8*/ /* interrupt register */
140: volatile u_int8_t imr; /*9*/ /* interrupt mask register */
141: volatile u_int8_t pr; /*10*/ /* poll register */
142: volatile u_int8_t biucc; /*11*/ /* biu config control */
143: volatile u_int8_t fifocc; /*12*/ /* fifo config control */
144: volatile u_int8_t maccc; /*13*/ /* mac config control */
145: volatile u_int8_t plscc; /*14*/ /* pls config control */
146: volatile u_int8_t phycc; /*15*/ /* phy config control */
147: volatile u_int8_t chipid1; /*16*/ /* chipid, low byte */
148: volatile u_int8_t chipid2; /*17*/ /* chipid, high byte */
149: volatile u_int8_t iac; /*18*/ /* internal address config */
150: volatile u_int8_t _reserved0; /*19*/ /* reserved */
151: volatile u_int8_t ladrf; /*20*/ /* logical address filter */
152: volatile u_int8_t padr; /*21*/ /* physical address */
153: volatile u_int8_t _reserved1; /*22*/ /* reserved */
154: volatile u_int8_t _reserved2; /*23*/ /* reserved */
155: volatile u_int8_t mpc; /*24*/ /* missed packet count */
156: volatile u_int8_t _reserved3; /*25*/ /* reserved */
157: volatile u_int8_t rntpc; /*26*/ /* runt packet count */
158: volatile u_int8_t rcvcc; /*27*/ /* receive collision count */
159: volatile u_int8_t _reserved4; /*28*/ /* reserved */
160: volatile u_int8_t utr; /*29*/ /* user test register */
161: volatile u_int8_t rtr1; /*30*/ /* reserved test register 1 */
162: volatile u_int8_t rtr2; /*31*/ /* reserved test register 2 */
163: };
164:
165: /* qe_mregs.xmtfc: transmit frame control. */
166: #define QE_MR_XMTFC_DRETRY 0x80 /* disable retries */
167: #define QE_MR_XMTFC_DXMTFCS 0x08 /* disable tx fcs */
168: #define QE_MR_XMTFC_APADXMT 0x01 /* enable auto padding */
169:
170: /* qe_mregs.xmtfs: transmit frame status. */
171: #define QE_MR_XMTFS_XMTSV 0x80 /* tx valid */
172: #define QE_MR_XMTFS_UFLO 0x40 /* tx underflow */
173: #define QE_MR_XMTFS_LCOL 0x20 /* tx late collision */
174: #define QE_MR_XMTFS_MORE 0x10 /* tx > 1 retries */
175: #define QE_MR_XMTFS_ONE 0x08 /* tx 1 retry */
176: #define QE_MR_XMTFS_DEFER 0x04 /* tx pkt deferred */
177: #define QE_MR_XMTFS_LCAR 0x02 /* tx carrier lost */
178: #define QE_MR_XMTFS_RTRY 0x01 /* tx retry error */
179:
180: /* qe_mregs.xmtrc: transmit retry count. */
181: #define QE_MR_XMTRC_EXDEF 0x80 /* tx excess defers */
182: #define QE_MR_XMTRC_XMTRC 0x0f /* tx retry count mask */
183:
184: /* qe_mregs.rcvfc: receive frame control. */
185: #define QE_MR_RCVFC_LLRCV 0x08 /* rx low latency */
186: #define QE_MR_RCVFC_MR 0x04 /* rx addr match/reject */
187: #define QE_MR_RCVFC_ASTRPRCV 0x01 /* rx auto strip */
188:
189: /* qe_mregs.rcvfs: receive frame status. */
190: #define QE_MR_RCVFS_OFLO 0x80 /* rx overflow */
191: #define QE_MR_RCVFS_CLSN 0x40 /* rx late collision */
192: #define QE_MR_RCVFS_FRAM 0x20 /* rx framing error */
193: #define QE_MR_RCVFS_FCS 0x10 /* rx fcs error */
194: #define QE_MR_RCVFS_RCVCNT 0x0f /* rx msg byte count mask */
195:
196: /* qe_mregs.fifofc: fifo frame count. */
197: #define QE_MR_FIFOFC_RCVFC 0xf0 /* rx fifo frame count */
198: #define QE_MR_FIFOFC_XMTFC 0x0f /* tx fifo frame count */
199:
200: /* qe_mregs.ir: interrupt register. */
201: #define QE_MR_IR_JAB 0x80 /* jabber error */
202: #define QE_MR_IR_BABL 0x40 /* babble error */
203: #define QE_MR_IR_CERR 0x20 /* collision error */
204: #define QE_MR_IR_RCVCCO 0x10 /* collision cnt overflow */
205: #define QE_MR_IR_RNTPCO 0x08 /* runt pkt cnt overflow */
206: #define QE_MR_IR_MPCO 0x04 /* miss pkt cnt overflow */
207: #define QE_MR_IR_RCVINT 0x02 /* packet received */
208: #define QE_MR_IR_XMTINT 0x01 /* packet transmitted */
209:
210: /* qe_mregs.imr: interrupt mask register. */
211: #define QE_MR_IMR_JABM 0x80 /* jabber errors */
212: #define QE_MR_IMR_BABLM 0x40 /* babble errors */
213: #define QE_MR_IMR_CERRM 0x20 /* collision errors */
214: #define QE_MR_IMR_RCVCCOM 0x10 /* rx collision count oflow */
215: #define QE_MR_IMR_RNTPCOM 0x08 /* runt pkt cnt ovrflw */
216: #define QE_MR_IMR_MPCOM 0x04 /* miss pkt cnt ovrflw */
217: #define QE_MR_IMR_RCVINTM 0x02 /* rx interrupts */
218: #define QE_MR_IMR_XMTINTM 0x01 /* tx interrupts */
219:
220: /* qe_mregs.pr: poll register. */
221: #define QE_MR_PR_XMTSV 0x80 /* tx status is valid */
222: #define QE_MR_PR_TDTREQ 0x40 /* tx data xfer request */
223: #define QE_MR_PR_RDTREQ 0x20 /* rx data xfer request */
224:
225: /* qe_mregs.biucc: biu config control. */
226: #define QE_MR_BIUCC_BSWAP 0x40 /* byte swap */
227: #define QE_MR_BIUCC_4TS 0x00 /* 4byte xmit start point */
228: #define QE_MR_BIUCC_16TS 0x10 /* 16byte xmit start point */
229: #define QE_MR_BIUCC_64TS 0x20 /* 64byte xmit start point */
230: #define QE_MR_BIUCC_112TS 0x30 /* 112byte xmit start point */
231: #define QE_MR_BIUCC_SWRST 0x01 /* sw-reset mace */
232:
233: /* qe_mregs.fifocc: fifo config control. */
234: #define QE_MR_FIFOCC_TXF8 0x00 /* tx fifo 8 write cycles */
235: #define QE_MR_FIFOCC_TXF32 0x80 /* tx fifo 32 write cycles */
236: #define QE_MR_FIFOCC_TXF16 0x40 /* tx fifo 16 write cycles */
237: #define QE_MR_FIFOCC_RXF64 0x20 /* rx fifo 64 write cycles */
238: #define QE_MR_FIFOCC_RXF32 0x10 /* rx fifo 32 write cycles */
239: #define QE_MR_FIFOCC_RXF16 0x00 /* rx fifo 16 write cycles */
240: #define QE_MR_FIFOCC_TFWU 0x08 /* tx fifo watermark update */
241: #define QE_MR_FIFOCC_RFWU 0x04 /* rx fifo watermark update */
242: #define QE_MR_FIFOCC_XMTBRST 0x02 /* tx burst enable */
243: #define QE_MR_FIFOCC_RCVBRST 0x01 /* rx burst enable */
244:
245: /* qe_mregs.maccc: mac config control. */
246: #define QE_MR_MACCC_PROM 0x80 /* promiscuous mode enable */
247: #define QE_MR_MACCC_DXMT2PD 0x40 /* tx 2part deferral enable */
248: #define QE_MR_MACCC_EMBA 0x20 /* modified backoff enable */
249: #define QE_MR_MACCC_DRCVPA 0x08 /* rx physical addr disable */
250: #define QE_MR_MACCC_DRCVBC 0x04 /* rx broadcast disable */
251: #define QE_MR_MACCC_ENXMT 0x02 /* enable transmitter */
252: #define QE_MR_MACCC_ENRCV 0x01 /* enable receiver */
253:
254: /* qe_mregs.plscc: pls config control. */
255: #define QE_MR_PLSCC_XMTSEL 0x08 /* tx mode select */
256: #define QE_MR_PLSCC_PORTMASK 0x06 /* media mask */
257: #define QE_MR_PLSCC_GPSI 0x06 /* use gpsi connector */
258: #define QE_MR_PLSCC_DAI 0x04 /* use dai connector */
259: #define QE_MR_PLSCC_TP 0x02 /* use twistedpair connector */
260: #define QE_MR_PLSCC_AUI 0x00 /* use aui connector */
261: #define QE_MR_PLSCC_ENPLSIO 0x01 /* pls i/o enable */
262:
263: /* qe_mregs.phycc: phy config control. */
264: #define QE_MR_PHYCC_LNKFL 0x80 /* link fail */
265: #define QE_MR_PHYCC_DLNKTST 0x40 /* disable link test logic */
266: #define QE_MR_PHYCC_REVPOL 0x20 /* rx polarity */
267: #define QE_MR_PHYCC_DAPC 0x10 /* autopolaritycorrect disab */
268: #define QE_MR_PHYCC_LRT 0x08 /* select low threshold */
269: #define QE_MR_PHYCC_ASEL 0x04 /* connector port auto-sel */
270: #define QE_MR_PHYCC_RWAKE 0x02 /* remote wakeup */
271: #define QE_MR_PHYCC_AWAKE 0x01 /* auto wakeup */
272:
273: /* qe_mregs.iac: internal address config. */
274: #define QE_MR_IAC_ADDRCHG 0x80 /* start address change */
275: #define QE_MR_IAC_PHYADDR 0x04 /* physical address reset */
276: #define QE_MR_IAC_LOGADDR 0x02 /* logical address reset */
277:
278: /* qe_mregs.utr: user test register. */
279: #define QE_MR_UTR_RTRE 0x80 /* enable resv test register */
280: #define QE_MR_UTR_RTRD 0x40 /* disab resv test register */
281: #define QE_MR_UTR_RPA 0x20 /* accept runt packets */
282: #define QE_MR_UTR_FCOLL 0x10 /* force collision status */
283: #define QE_MR_UTR_RCVSFCSE 0x08 /* enable fcs on rx */
284: #define QE_MR_UTR_INTLOOPM 0x06 /* Internal loopback w/mandec */
285: #define QE_MR_UTR_INTLOOP 0x04 /* Internal loopback */
286: #define QE_MR_UTR_EXTLOOP 0x02 /* external loopback */
287: #define QE_MR_UTR_NOLOOP 0x00 /* no loopback */
288:
289: /*
290: * QE receive descriptor
291: */
292: struct qe_rxd {
293: volatile u_int32_t rx_flags; /* rx descriptor flags */
294: volatile u_int32_t rx_addr; /* rx buffer address */
295: };
296:
297: #define QE_RXD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */
298: #define QE_RXD_UPDATE 0x10000000 /* being updated? */
299: #define QE_RXD_LENGTH 0x000007ff /* packet length */
300:
301: /*
302: * QE transmit descriptor
303: */
304: struct qe_txd {
305: volatile u_int32_t tx_flags; /* tx descriptor flags */
306: volatile u_int32_t tx_addr; /* tx buffer address */
307: };
308:
309: #define QE_TXD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */
310: #define QE_TXD_SOP 0x40000000 /* start of packet marker */
311: #define QE_TXD_EOP 0x20000000 /* end of packet marker */
312: #define QE_TXD_UPDATE 0x10000000 /* being updated? */
313: #define QE_TXD_LENGTH 0x000007ff /* packet length */
314:
315: /* Buffer and Ring sizes: fixed ring size */
316: #define QE_TX_RING_MAXSIZE 256 /* maximum tx ring size */
317: #define QE_RX_RING_MAXSIZE 256 /* maximum rx ring size */
318: #define QE_TX_RING_SIZE 16 /* power of 2, <= MAXSIZE */
319: #define QE_RX_RING_SIZE 16 /* power of 2, <= MAXSIZE */
320: #define QE_PKT_BUF_SZ 2048
321:
322: #define QE_TX_RING_MAXMASK (QE_TX_RING_MAXSIZE-1)
323: #define QE_RX_RING_MAXMASK (QE_RX_RING_MAXSIZE-1)
324: #define QE_TX_RING_MASK (QE_TX_RING_SIZE-1)
325: #define QE_RX_RING_MASK (QE_RX_RING_SIZE-1)
326:
327: /*
328: * QE descriptor rings
329: */
330: struct qe_desc {
331: struct qe_rxd qe_rxd[QE_RX_RING_MAXSIZE];
332: struct qe_txd qe_txd[QE_TX_RING_MAXSIZE];
333: };
334:
335: /*
336: * QE packet buffers
337: */
338: struct qe_bufs {
339: char rx_buf[QE_RX_RING_SIZE][QE_PKT_BUF_SZ];
340: char tx_buf[QE_TX_RING_SIZE][QE_PKT_BUF_SZ];
341: };
342:
343: #define MC_POLY_LE 0xedb88320 /* mcast crc, little endian */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to qereg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / sparc / dev