Annotation of sys/arch/sparc/dev/qecreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: qecreg.h,v 1.4 2003/06/02 15:54:22 deraadt Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 1998 Theo de Raadt and Jason L. Wright.
! 5: * All rights reserved.
! 6: *
! 7: * Redistribution and use in source and binary forms, with or without
! 8: * modification, are permitted provided that the following conditions
! 9: * are met:
! 10: * 1. Redistributions of source code must retain the above copyright
! 11: * notice, this list of conditions and the following disclaimer.
! 12: * 2. Redistributions in binary form must reproduce the above copyright
! 13: * notice, this list of conditions and the following disclaimer in the
! 14: * documentation and/or other materials provided with the distribution.
! 15: *
! 16: * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
! 17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 19: * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! 20: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 21: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 22: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 23: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 24: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 25: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 26: */
! 27:
! 28: /* QEC registers */
! 29: struct qecregs {
! 30: volatile u_int32_t ctrl; /* control */
! 31: volatile u_int32_t stat; /* status */
! 32: volatile u_int32_t psize; /* packet size */
! 33: volatile u_int32_t msize; /* local-mem size (64K) */
! 34: volatile u_int32_t rsize; /* receive partition size */
! 35: volatile u_int32_t tsize; /* transmit partition size */
! 36: };
! 37:
! 38: /* qecregs.ctrl: control. */
! 39: #define QEC_CTRL_MODEMASK 0xf0000000 /* QEC mode: qe or be */
! 40: #define QEC_CTRL_MMODE 0x40000000 /* MACE qec mode */
! 41: #define QEC_CTRL_BMODE 0x10000000 /* BE qec mode */
! 42: #define QEC_CTRL_EPAR 0x00000020 /* enable parity */
! 43: #define QEC_CTRL_ACNTRL 0x00000018 /* sbus arbitration control */
! 44: #define QEC_CTRL_B64 0x00000004 /* 64 byte dvma bursts */
! 45: #define QEC_CTRL_B32 0x00000002 /* 32 byte dvma bursts */
! 46: #define QEC_CTRL_B16 0x00000000 /* 16 byte dvma bursts */
! 47: #define QEC_CTRL_RESET 0x00000001 /* reset the qec */
! 48:
! 49: /* qecregs.stat: status. */
! 50: #define QEC_STAT_TX 0x00000008 /* bigmac transmit irq */
! 51: #define QEC_STAT_RX 0x00000004 /* bigmac receive irq */
! 52: #define QEC_STAT_BM 0x00000002 /* bigmac qec irq */
! 53: #define QEC_STAT_ER 0x00000001 /* bigmac error irq */
! 54:
! 55: /* qecregs.stat: packet size. */
! 56: #define QEC_PSIZE_2048 0x00 /* 2k packet size */
! 57: #define QEC_PSIZE_4096 0x01 /* 4k packet size */
! 58: #define QEC_PSIZE_6144 0x10 /* 6k packet size */
! 59: #define QEC_PSIZE_8192 0x11 /* 8k packet size */
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