Annotation of sys/arch/sparc/dev/hmereg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: hmereg.h,v 1.12 2005/02/22 20:44:26 brad Exp $ */
2:
3: /*
4: * Copyright (c) 1998 Jason L. Wright (jason@thought.net)
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
25: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26: * POSSIBILITY OF SUCH DAMAGE.
27: */
28:
29: #define HME_DEFAULT_JSIZE 4
30: #define HME_DEFAULT_IPKT_GAP0 16
31: #define HME_DEFAULT_IPKT_GAP1 8
32: #define HME_DEFAULT_IPKT_GAP2 4
33:
34: /* global registers */
35: struct hme_gr {
36: volatile u_int32_t reset; /* reset tx/rx */
37: volatile u_int32_t cfg; /* config */
38: volatile u_int32_t _padding[62]; /* unused */
39: volatile u_int32_t stat; /* intr status */
40: volatile u_int32_t imask; /* intr mask */
41: };
42:
43: /* hme_gr.reset (software reset register) */
44: #define GR_RESET_ETX 0x01 /* reset external tx */
45: #define GR_RESET_ERX 0x02 /* reset external rx */
46: #define GR_RESET_ALL (GR_RESET_ETX | GR_RESET_ERX)
47:
48: /* hme_gr.cfg (configuration register) */
49: #define GR_CFG_BURSTMSK 0x03 /* burst mask */
50: #define GR_CFG_BURST16 0x00 /* 16 byte bursts */
51: #define GR_CFG_BURST32 0x01 /* 32 byte bursts */
52: #define GR_CFG_BURST64 0x02 /* 32 byte bursts */
53: #define GR_CFG_64BIT 0x04
54: #define GR_CFG_PARITY 0x08
55: #define GR_CFG_RESV 0x10
56:
57: /* hme_gr.stat (interrupt status register) */
58: #define GR_STAT_GOTFRAME 0x00000001 /* frame received */
59: #define GR_STAT_RCNTEXP 0x00000002 /* rx frame count expired */
60: #define GR_STAT_ACNTEXP 0x00000004 /* align error count expired */
61: #define GR_STAT_CCNTEXP 0x00000008 /* crc error count expired */
62: #define GR_STAT_LCNTEXP 0x00000010 /* length error count expired */
63: #define GR_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */
64: #define GR_STAT_CVCNTEXP 0x00000040 /* code violation counter expired */
65: #define GR_STAT_STSTERR 0x00000080 /* xif sqe test failed */
66: #define GR_STAT_SENTFRAME 0x00000100 /* frame sent */
67: #define GR_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */
68: #define GR_STAT_MAXPKTERR 0x00000400 /* max-packet size error */
69: #define GR_STAT_NCNTEXP 0x00000800 /* normal collision count expired */
70: #define GR_STAT_ECNTEXP 0x00001000 /* excess collision count expired */
71: #define GR_STAT_LCCNTEXP 0x00002000 /* late collision count expired */
72: #define GR_STAT_FCNTEXP 0x00004000 /* first collision count expired */
73: #define GR_STAT_DTIMEXP 0x00008000 /* defer timer expired */
74: #define GR_STAT_RXTOHOST 0x00010000 /* pkt moved from rx fifo->memory */
75: #define GR_STAT_NORXD 0x00020000 /* out of receive descriptors */
76: #define GR_STAT_RXERR 0x00040000 /* rx dma error */
77: #define GR_STAT_RXLATERR 0x00080000 /* late error during rx dma */
78: #define GR_STAT_RXPERR 0x00100000 /* parity error during rx dma */
79: #define GR_STAT_RXTERR 0x00200000 /* tag error during rx dma */
80: #define GR_STAT_EOPERR 0x00400000 /* tx descriptor did not set EOP */
81: #define GR_STAT_MIFIRQ 0x00800000 /* mif needs attention */
82: #define GR_STAT_HOSTTOTX 0x01000000 /* pkt moved from memory->tx fifo */
83: #define GR_STAT_TXALL 0x02000000 /* all pkts in fifo transmitted */
84: #define GR_STAT_TXEACK 0x04000000 /* error during tx dma */
85: #define GR_STAT_TXLERR 0x08000000 /* late error during tx dma */
86: #define GR_STAT_TXPERR 0x10000000 /* parity error during tx dma */
87: #define GR_STAT_TXTERR 0x20000000 /* tag error durig tx dma */
88: #define GR_STAT_SLVERR 0x40000000 /* pio access error */
89: #define GR_STAT_SLVPERR 0x80000000 /* pio access parity error */
90:
91: /* all the errors to worry about */
92: #define GR_STAT_ALL_ERRORS \
93: (GR_STAT_SLVPERR | GR_STAT_SLVERR | GR_STAT_TXTERR | \
94: GR_STAT_TXPERR | GR_STAT_TXLERR | GR_STAT_TXEACK | \
95: GR_STAT_EOPERR | GR_STAT_RXTERR | GR_STAT_RXPERR | \
96: GR_STAT_RXLATERR | GR_STAT_RXERR | GR_STAT_NORXD | \
97: GR_STAT_DTIMEXP | GR_STAT_FCNTEXP | GR_STAT_LCCNTEXP | \
98: GR_STAT_ECNTEXP | GR_STAT_NCNTEXP | GR_STAT_MAXPKTERR | \
99: GR_STAT_TFIFO_UND | GR_STAT_STSTERR | GR_STAT_CVCNTEXP | \
100: GR_STAT_RFIFOVF | GR_STAT_LCNTEXP | GR_STAT_CCNTEXP | \
101: GR_STAT_ACNTEXP)
102:
103: #define GR_STAT_BITS \
104: "\20\1RX\2RCNT\3ACNT\4CCNT\5LCNT\6RFIFO\7CVCNT\10STST" \
105: "\11TX\12TFIFO\13MAXPKT\14NCNT\15ECNT\16LCCNT\17FCNT" \
106: "\20DTIME\21RXHOST\22NORXD\23RXE\24EXLATE\25RXP\26RXT\27EOP" \
107: "\30MIF\31TXHOST\32TXALL\33TXE\34TXL\35TXP\36TXT\37SLV" \
108: "\40SLVP"
109:
110: /* hme_gr.stat (interrupt status register) */
111: #define GR_IMASK_GOTFRAME 0x00000001 /* frame received */
112: #define GR_IMASK_RCNTEXP 0x00000002 /* rx frame count expired */
113: #define GR_IMASK_ACNTEXP 0x00000004 /* align error count expired */
114: #define GR_IMASK_CCNTEXP 0x00000008 /* crc error count expired */
115: #define GR_IMASK_LCNTEXP 0x00000010 /* length error count expired */
116: #define GR_IMASK_RFIFOVF 0x00000020 /* rx fifo overflow */
117: #define GR_IMASK_CVCNTEXP 0x00000040 /* code violation count expired */
118: #define GR_IMASK_STSTERR 0x00000080 /* xif sqe test failed */
119: #define GR_IMASK_SENTFRAME 0x00000100 /* frame sent */
120: #define GR_IMASK_TFIFO_UND 0x00000200 /* tx fifo underrun */
121: #define GR_IMASK_MAXPKTERR 0x00000400 /* max-packet size error */
122: #define GR_IMASK_NCNTEXP 0x00000800 /* normal collision count expired */
123: #define GR_IMASK_ECNTEXP 0x00001000 /* excess collision count expired */
124: #define GR_IMASK_LCCNTEXP 0x00002000 /* late collision count expired */
125: #define GR_IMASK_FCNTEXP 0x00004000 /* first collision count expired */
126: #define GR_IMASK_DTIMEXP 0x00008000 /* defer timer expired */
127: #define GR_IMASK_RXTOHOST 0x00010000 /* pkt moved from rx fifo->memory */
128: #define GR_IMASK_NORXD 0x00020000 /* out of receive descriptors */
129: #define GR_IMASK_RXERR 0x00040000 /* rx dma error */
130: #define GR_IMASK_RXLATERR 0x00080000 /* late error during rx dma */
131: #define GR_IMASK_RXPERR 0x00100000 /* parity error during rx dma */
132: #define GR_IMASK_RXTERR 0x00200000 /* tag error during rx dma */
133: #define GR_IMASK_EOPERR 0x00400000 /* tx descriptor did not set EOP */
134: #define GR_IMASK_MIFIRQ 0x00800000 /* mif needs attention */
135: #define GR_IMASK_HOSTTOTX 0x01000000 /* pkt moved from memory->tx fifo */
136: #define GR_IMASK_TXALL 0x02000000 /* all pkts in fifo transmitted */
137: #define GR_IMASK_TXEACK 0x04000000 /* error during tx dma */
138: #define GR_IMASK_TXLERR 0x08000000 /* late error during tx dma */
139: #define GR_IMASK_TXPERR 0x10000000 /* parity error during tx dma */
140: #define GR_IMASK_TXTERR 0x20000000 /* tag error during tx dma */
141: #define GR_IMASK_SLVERR 0x40000000 /* pio access error */
142: #define GR_IMASK_SLVPERR 0x80000000 /* PIO access parity error */
143:
144: /*
145: * external transmitter registers
146: */
147: struct hme_txr {
148: volatile u_int32_t tx_pnding; /* tx pending/wakeup */
149: volatile u_int32_t cfg; /* tx cfg */
150: volatile u_int32_t tx_ring; /* tx ring ptr */
151: volatile u_int32_t tx_bbase; /* tx buffer base */
152: volatile u_int32_t tx_bdisp; /* tx buffer displacement */
153: volatile u_int32_t tx_fifo_wptr; /* tx fifo write pointer */
154: volatile u_int32_t tx_fifo_swptr; /* tx fifo write ptr (shadow) */
155: volatile u_int32_t tx_fifo_rptr; /* tx fifo read pointer */
156: volatile u_int32_t tx_fifo_srptr; /* tx fifo read ptr (shadow) */
157: volatile u_int32_t tx_fifo_pcnt; /* tx fifo packet counter */
158: volatile u_int32_t smachine; /* tx state machine */
159: volatile u_int32_t tx_rsize; /* tx ring size */
160: volatile u_int32_t tx_bptr; /* tx buffer pointer */
161: };
162:
163: /* hme_txr.tx_pnding (tx pending/wakeup) */
164: #define TXR_TP_DMAWAKEUP 0x00000001 /* Restart transmit dma */
165:
166: /* hme_txr.tx_cfg (tx configuration) */
167: #define TXR_CFG_DMAENABLE 0x00000001 /* enable tx dma */
168: #define TXR_CFG_FIFOTHRESH 0x000003fe /* tx fifo threshold */
169: #define TXR_CFG_IRQDAFTER 0x00000400 /* intr after tx-fifo empty */
170: #define TXR_CFG_IRQDBEFORE 0x00000000 /* intr before tx-fifo empty */
171: #define TXR_RSIZE_SHIFT 4
172:
173: /*
174: * external receiver registers
175: */
176: struct hme_rxr {
177: volatile u_int32_t cfg; /* rx cfg */
178: volatile u_int32_t rx_ring; /* rx ring pointer */
179: volatile u_int32_t rx_bptr; /* rx buffer ptr */
180: volatile u_int32_t rx_fifo_wptr; /* rx fifo write ptr */
181: volatile u_int32_t rx_fifo_swptr; /* rx fifo write ptr (shadow) */
182: volatile u_int32_t rx_fifo_rptr; /* rx fifo read ptr */
183: volatile u_int32_t rx_fifo_srptr; /* rx fifo read ptr (shadow) */
184: volatile u_int32_t smachine; /* rx state machine */
185: };
186:
187: /* hme_rxr.rx_cfg (rx configuration) */
188: #define RXR_CFG_DMAENABLE 0x00000001 /* rx dma enable */
189: #define RXR_CFG_reserved1 0x00000006 /* reserved bits */
190: #define RXR_CFG_BYTEOFFSET 0x00000038 /* rx first byte offset */
191: #define RXR_CFG_reserved2 0x000001c0 /* reserved bits */
192: #define RXR_CFG_RINGSIZE32 0x00000000 /* rx descptr ring size: 32 */
193: #define RXR_CFG_RINGSIZE64 0x00000200 /* rx descptr ring size: 64 */
194: #define RXR_CFG_RINGSIZE128 0x00000400 /* rx descptr ring size: 128 */
195: #define RXR_CFG_RINGSIZE256 0x00000600 /* rx descptr ring size: 128 */
196: #define RXR_CFG_reserved3 0x0000f800 /* reserved bits */
197: #define RXR_CFG_CSUMSTART 0x007f0000 /* rx offset of checksum */
198: #define RXR_CFG_CSUM_SHIFT 16
199:
200: /*
201: * configuration registers
202: */
203: struct hme_cr {
204: volatile u_int32_t xif_cfg; /* xif configuration reg */
205: volatile u_int32_t _padding[129]; /* reserved */
206: volatile u_int32_t tx_swreset; /* tx software reset */
207: volatile u_int32_t tx_cfg; /* tx configuration reg */
208: volatile u_int32_t ipkt_gap1; /* interpacket gap 1 */
209: volatile u_int32_t ipkt_gap2; /* interpacket gap 2 */
210: volatile u_int32_t attempt_limit; /* tx attempt limit */
211: volatile u_int32_t stime; /* tx slot time */
212: volatile u_int32_t preamble_len; /* len of tx preamble */
213: volatile u_int32_t preamble_patt; /* tx preamble pattern */
214: volatile u_int32_t tx_sframedelim; /* tx frame delimiter */
215: volatile u_int32_t jsize; /* tx jam size */
216: volatile u_int32_t tx_pkt_max; /* tx maximum pkt size */
217: volatile u_int32_t tx_pkt_min; /* tx minimum pkt size */
218: volatile u_int32_t peak_attempt; /* tx peak counter */
219: volatile u_int32_t dt_ctr; /* tx defer counter */
220: volatile u_int32_t nc_ctr; /* tx normal collision cntr */
221: volatile u_int32_t fc_ctr; /* tx first collision cntr */
222: volatile u_int32_t ex_ctr; /* tx execess collision cntr */
223: volatile u_int32_t lt_ctr; /* tx late collision cntr */
224: volatile u_int32_t rand_seed; /* tx random seed */
225: volatile u_int32_t tx_smachine; /* tx state machine */
226: volatile u_int32_t _padding2[44]; /* reserved */
227: volatile u_int32_t rx_swreset; /* rx software reset */
228: volatile u_int32_t rx_cfg; /* rx configuration */
229: volatile u_int32_t rx_pkt_max; /* rx maximum pkt size */
230: volatile u_int32_t rx_pkt_min; /* rx minimum pkt size */
231: volatile u_int32_t mac_addr2; /* macaddress register2 (MSB) */
232: volatile u_int32_t mac_addr1; /* macaddress register1 */
233: volatile u_int32_t mac_addr0; /* macaddress register0 (LSB) */
234: volatile u_int32_t fr_ctr; /* rx frame counter */
235: volatile u_int32_t gle_ctr; /* rx giant counter */
236: volatile u_int32_t unale_ctr; /* rx unaligned error cntr */
237: volatile u_int32_t rcrce_ctr; /* rx crc error cntr */
238: volatile u_int32_t rx_smachine; /* rx state machine */
239: volatile u_int32_t rx_cvalid; /* rx code violation */
240: volatile u_int32_t _padding3; /* reserved */
241: volatile u_int32_t htable3; /* hash table 3 */
242: volatile u_int32_t htable2; /* hash table 2 */
243: volatile u_int32_t htable1; /* hash table 1 */
244: volatile u_int32_t htable0; /* hash table 0 */
245: volatile u_int32_t afilter2; /* address filter 2 */
246: volatile u_int32_t afilter1; /* address filter 1 */
247: volatile u_int32_t afilter0; /* address filter 0 */
248: volatile u_int32_t afilter_mask; /* address filter mask */
249: };
250:
251: /* BigMac XIF config register. */
252: #define CR_XCFG_ODENABLE 0x00000001 /* Output driver enable */
253: #define CR_XCFG_XLBACK 0x00000002 /* Loopback-mode XIF enable */
254: #define CR_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */
255: #define CR_XCFG_MIIDISAB 0x00000008 /* MII receive buffer disable */
256: #define CR_XCFG_SQENABLE 0x00000010 /* SQE test enable */
257: #define CR_XCFG_SQETWIN 0x000003e0 /* SQE time window */
258: #define CR_XCFG_LANCE 0x00000010 /* Lance mode enable */
259: #define CR_XCFG_LIPG0 0x000003e0 /* Lance mode IPG0 */
260:
261: /* BigMac transmit config register. */
262: #define CR_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
263: #define CR_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
264: #define CR_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
265: #define CR_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
266: #define CR_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
267: #define CR_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
268: #define CR_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */
269:
270: /* BigMac receive config register. */
271: #define CR_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
272: #define CR_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
273: #define CR_RXCFG_PMISC 0x00000040 /* Enable promiscous mode */
274: #define CR_RXCFG_DERR 0x00000080 /* Disable error checking */
275: #define CR_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
276: #define CR_RXCFG_ME 0x00000200 /* Receive packets addressed to me */
277: #define CR_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
278: #define CR_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
279: #define CR_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
280:
281: struct hme_tcvr {
282: volatile u_int32_t bb_clock; /* bit bang clock */
283: volatile u_int32_t bb_data; /* bit bang data */
284: volatile u_int32_t bb_oenab; /* bit bang output enable */
285: volatile u_int32_t frame; /* frame control & data */
286: volatile u_int32_t cfg; /* MIF configuration */
287: volatile u_int32_t int_mask; /* MIF interrupt mask */
288: volatile u_int32_t status; /* MIF status */
289: volatile u_int32_t smachine; /* MIF state machine */
290: };
291:
292: #define FRAME_WRITE 0x50020000 /* start a frame write */
293: #define FRAME_READ 0x60020000 /* start a frame read */
294: #define TCVR_FAILURE 0x80000000 /* impossible value */
295:
296: /* Transceiver config register */
297: #define TCVR_CFG_PSELECT 0x00000001 /* select PHY */
298: #define TCVR_CFG_PENABLE 0x00000002 /* enable MIF polling */
299: #define TCVR_CFG_BENABLE 0x00000004 /* enable bit bang */
300: #define TCVR_CFG_PREGADDR 0x000000f8 /* poll register addr */
301: #define TCVR_CFG_MDIO0 0x00000100 /* MDIO zero, data/attached */
302: #define TCVR_CFG_MDIO1 0x00000200 /* MDIO one, data/attached */
303: #define TCVR_CFG_PDADDR 0x00007c00 /* device phy addr polling */
304:
305: /* Here are some PHY addresses. */
306: #define TCVR_PHYADDR_ETX 0 /* external transceiver */
307: #define TCVR_PHYADDR_ITX 1 /* internal transceiver */
308:
309: /* Transceiver status register */
310: #define TCVR_STAT_BASIC 0xffff0000 /* The "basic" part */
311: #define TCVR_STAT_NORMAL 0x0000ffff /* The "non-basic" part */
312:
313: /* hme flags */
314: #define HME_FLAG_POLL 0x00000001 /* polling mif? */
315: #define HME_FLAG_FENABLE 0x00000002 /* MII frame enabled? */
316: #define HME_FLAG_LANCE 0x00000004 /* Lance mode IPG0? */
317: #define HME_FLAG_RXENABLE 0x00000008 /* Receiver enabled? */
318: #define HME_FLAG_AUTO 0x00000010 /* Auto-Neg? 0 = force */
319: #define HME_FLAG_FULL 0x00000020 /* Full duplex enabled? */
320: #define HME_FLAG_MACFULL 0x00000040 /* Full duplex in the MAC? */
321: #define HME_FLAG_POLLENABLE 0x00000080 /* Try MIF polling? */
322: #define HME_FLAG_RXCV 0x00000100 /* RXCV enable - XXX */
323: #define HME_FLAG_INIT 0x00000200 /* Initialized once? */
324: #define HME_FLAG_LINKUP 0x00000400 /* Is link up? */
325:
326: #define HME_FLAG_20_21 \
327: (HME_FLAG_POLLENABLE | HME_FLAG_FENABLE)
328: #define HME_FLAG_NOT_A0 \
329: (HME_FLAG_POLLENABLE | HME_FLAG_FENABLE | HME_FLAG_LANCE | HME_FLAG_RXCV)
330:
331: /*
332: * Transceiver type
333: */
334: #define HME_TCVR_EXTERNAL 0
335: #define HME_TCVR_INTERNAL 1
336: #define HME_TCVR_NONE 2
337:
338: struct hme_rxd {
339: volatile u_int32_t rx_flags;
340: volatile u_int32_t rx_addr;
341: };
342: #define HME_RXD_OWN 0x80000000 /* desc owner: 1=hw,0=sw */
343: #define HME_RXD_OVERFLOW 0x40000000 /* 1 = buffer over flow */
344: #define HME_RXD_SIZE 0x3fff0000 /* descriptor size */
345: #define HME_RXD_CSUM 0x0000ffff /* checksum mask */
346:
347: struct hme_txd {
348: volatile u_int32_t tx_flags;
349: volatile u_int32_t tx_addr;
350: };
351: #define HME_TXD_OWN 0x80000000 /* desc owner: 1=hw,0=sw */
352: #define HME_TXD_SOP 0x40000000 /* 1 = start of pkt */
353: #define HME_TXD_EOP 0x20000000 /* 1 = end of pkt */
354: #define HME_TXD_CSENABLE 0x10000000 /* 1 = use hw checksums */
355: #define HME_TXD_CSLOCATION 0x0ff00000 /* checksum location mask */
356: #define HME_TXD_CSBUFBEGIN 0x000fc000 /* checksum begin mask */
357: #define HME_TXD_SIZE 0x00003fff /* pkt size mask */
358:
359: #define HME_RX_RING_SIZE 32 /* Must be 32,64,128, or 256 */
360: #define HME_TX_RING_SIZE 32 /* 16<=x<=256 and div by 16 */
361: #define HME_RX_RING_MAX 256 /* maximum ring size: rx */
362: #define HME_TX_RING_MAX 256 /* maximum ring size: tx */
363: #define HME_RX_PKT_BUF_SZ 2048 /* size of a rx buffer */
364: #define HME_RX_OFFSET 2 /* packet offset */
365: #define HME_RX_CSUMLOC 0x00 /* checksum location */
366: #define HME_TX_PKT_BUF_SZ 1546 /* size of a tx buffer */
367: #define HME_RX_ALIGN_SIZE 64 /* XXX rx bufs must align 64 */
368: #define HME_RX_ALIGN_MASK (~(RX_ALIGN_SIZE - 1))
369:
370: struct hme_desc {
371: struct hme_rxd hme_rxd[HME_RX_RING_MAX];
372: struct hme_txd hme_txd[HME_TX_RING_MAX];
373: };
374:
375: struct hme_bufs {
376: char rx_buf[HME_RX_RING_SIZE][HME_RX_PKT_BUF_SZ];
377: char tx_buf[HME_TX_RING_SIZE][HME_TX_PKT_BUF_SZ];
378: };
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