Annotation of sys/arch/sparc/dev/fgareg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: fgareg.h,v 1.2 2003/06/02 18:40:59 jason Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
! 5: * All rights reserved.
! 6: *
! 7: * This software was developed by Jason L. Wright under contract with
! 8: * RTMX Incorporated (http://www.rtmx.com).
! 9: *
! 10: * Redistribution and use in source and binary forms, with or without
! 11: * modification, are permitted provided that the following conditions
! 12: * are met:
! 13: * 1. Redistributions of source code must retain the above copyright
! 14: * notice, this list of conditions and the following disclaimer.
! 15: * 2. Redistributions in binary form must reproduce the above copyright
! 16: * notice, this list of conditions and the following disclaimer in the
! 17: * documentation and/or other materials provided with the distribution.
! 18: *
! 19: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 20: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 21: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
! 22: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
! 23: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 24: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 25: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 26: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
! 27: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
! 28: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 29: * POSSIBILITY OF SUCH DAMAGE.
! 30: */
! 31:
! 32: /*
! 33: * Register definitions for Force Gate Array 5000
! 34: * Definitions from: "Force Gate Array-5000 Technical Reference Manual"
! 35: * revision 1, April 1995, Force Computers, Inc./GmbH.
! 36: */
! 37:
! 38: /*
! 39: * FGA Register structure.
! 40: * The register set takes up 512 bytes and is found in to sbus slot 5's
! 41: * address space (you can change that).
! 42: * Most of the bit registers use a negative logic sense: ie. writing
! 43: * a zero means "setting the bit" and writing a one means "clearing"
! 44: * the bit.
! 45: */
! 46: struct fga_regs {
! 47: volatile u_int32_t sbus_base; /* sbus base address reg */
! 48: volatile u_int32_t vme_range[16]; /* master range registers */
! 49: volatile u_int8_t _unused0[32];
! 50: volatile u_int8_t vme_master_cap[16];/* master capability */
! 51: volatile u_int8_t _unused1[8];
! 52: volatile u_int8_t sbus_ssel[8]; /* sbus slot select */
! 53: volatile u_int8_t _unused2[15];
! 54: volatile u_int8_t viack_emu1; /* vme intr ack emulation */
! 55: volatile u_int8_t _unused3[1];
! 56: volatile u_int8_t viack_emu2;
! 57: volatile u_int8_t _unused4[1];
! 58: volatile u_int8_t viack_emu3;
! 59: volatile u_int8_t _unused5[1];
! 60: volatile u_int8_t viack_emu4;
! 61: volatile u_int8_t _unused6[1];
! 62: volatile u_int8_t viack_emu5;
! 63: volatile u_int8_t _unused7[1];
! 64: volatile u_int8_t viack_emu6;
! 65: volatile u_int8_t _unused8[1];
! 66: volatile u_int8_t viack_emu7;
! 67: volatile u_int8_t _unused9[16];
! 68: volatile u_int8_t sbus_cap; /* sbus capabilities */
! 69: volatile u_int8_t sbus_retry_ctrl; /* sbus retry control */
! 70: volatile u_int8_t sbus_rerun_ctrl; /* sbus rerun control */
! 71: volatile u_int8_t sbus_cap2; /* sbus capabilities 2 */
! 72: volatile u_int32_t swpar; /* sbus write post err addr */
! 73: volatile u_int32_t slerr; /* sbus late err addr */
! 74: volatile u_int32_t _unused10;
! 75: volatile u_int8_t vme_base; /* vme slave base addr */
! 76: volatile u_int8_t vme_ext[3]; /* vme slave addr extension */
! 77: volatile u_int32_t sbus_range[3]; /* vme->sbus slave addr */
! 78: volatile u_int16_t ibox_addr; /* ibox address */
! 79: volatile u_int16_t ibox_ctrl; /* ibox control */
! 80: volatile u_int8_t fmb_ctrl; /* FMB control reg */
! 81: volatile u_int8_t fmb_addr; /* FMB addresss reg */
! 82: volatile u_int8_t _unused11[10];
! 83: volatile u_int8_t vme_cap; /* vme capabilities */
! 84: volatile u_int8_t vmebus_handshake; /* vme handshake mode */
! 85: volatile u_int8_t _unused12[2];
! 86: volatile u_int32_t vwpar; /* vme write post addr */
! 87: volatile u_int8_t _unused13[8];
! 88: volatile u_int16_t dma_ctrl; /* dma control */
! 89: volatile u_int8_t dma_mode; /* dma mode */
! 90: volatile u_int8_t dma_stat; /* dma status */
! 91: volatile u_int32_t dma_src; /* dma source address */
! 92: volatile u_int32_t dma_dst; /* dma destination address */
! 93: volatile u_int32_t dma_captl; /* dma capabilities/length */
! 94: volatile u_int8_t _unused14[32];
! 95: volatile u_int8_t mbox[16]; /* mailboxes */
! 96: volatile u_int8_t sem[48]; /* semaphores */
! 97: volatile u_int8_t _unused15[32];
! 98: volatile u_int8_t id[4]; /* revision/id register */
! 99: volatile u_int8_t gcsr; /* global control/status */
! 100: volatile u_int8_t _unused16[3];
! 101: volatile u_int8_t reset_stat; /* reset status */
! 102: volatile u_int8_t _unused17[24];
! 103: volatile u_int8_t virq_map[7]; /* vme->sbus irq mapping */
! 104: volatile u_int8_t mbox_irq_map[16];
! 105: volatile u_int8_t acfail_irq_map;
! 106: volatile u_int8_t sysfail_irq_map[2];
! 107: volatile u_int8_t abort_irq_map;
! 108: volatile u_int8_t dma_irq_map;
! 109: volatile u_int8_t wpe_irq_map;
! 110: volatile u_int8_t arb_irq_map;
! 111: volatile u_int8_t wdt_irq_map;
! 112: volatile u_int8_t slerr_irq_map;
! 113: volatile u_int8_t fmb_irq_map[2];
! 114: volatile u_int8_t ibox_irq_map;
! 115: volatile u_int8_t _unused18[20];
! 116: volatile u_int16_t mbox_stat; /* mailbox status */
! 117: volatile u_int8_t _unused19[2];
! 118: volatile u_int8_t arb_ctrl; /* arbitration control */
! 119: volatile u_int8_t req_ctrl; /* vme request control */
! 120: volatile u_int8_t bus_ctrl; /* vme bus control */
! 121: volatile u_int8_t _unused20[1];
! 122: volatile u_int8_t mcsr0; /* misc control/status */
! 123: volatile u_int8_t _unused21[3];
! 124: volatile u_int8_t mcsr1; /* misc control/status */
! 125: volatile u_int8_t wdt_restart; /* watchdog restart */
! 126: volatile u_int8_t _unused22[2];
! 127: volatile u_int32_t intr_stat; /* interrupt status */
! 128: volatile u_int8_t _unused23[20];
! 129: };
! 130:
! 131: /* sbus_base: sbus base address register */
! 132: #define SBUS_BASE_RMBA 0xffffe000 /* reg map base address */
! 133: #define SBUS_BASE_RMSS 0x00000007 /* reg map slot select bits */
! 134:
! 135: /* vme_range0..15: master range registers */
! 136: #define VME_RANGE_VMRCC 0xfff80000 /* master range compare code */
! 137: #define VME_RANGE_VMAE 0x00078000 /* master adr extension bits */
! 138: #define VME_RANGE_VMAT 0x00007ff8 /* master adr xlation bits */
! 139: #define VME_RANGE_WPEN 0x00000002 /* write posting enable */
! 140: #define VME_RANGE_DECEN 0x00000001 /* range decoding enable */
! 141:
! 142: /* vme_master_map0..15: master capability registers */
! 143: #define VME_MASTER_CAP_DATA 0xe0 /* data capabilities */
! 144: #define VME_MASTER_CAP_D8 0x00 /* vmebus D8 */
! 145: #define VME_MASTER_CAP_D16 0x20 /* vmebus D16 */
! 146: #define VME_MASTER_CAP_D32 0x40 /* vmebus D32 */
! 147: #define VME_MASTER_CAP_DBLT 0x60 /* vmebus BLT */
! 148: #define VME_MASTER_CAP_DMBLT 0x80 /* vmebus MBLT */
! 149: #define VME_MASTER_CAP_ADDR 0x1c /* addr capabilities */
! 150: #define VME_MASTER_CAP_A16 0x00 /* vmebus A16 */
! 151: #define VME_MASTER_CAP_A24 0x04 /* vmebus A24 */
! 152: #define VME_MASTER_CAP_A32 0x08 /* vmebus A32 */
! 153: #define FVME_MAX_RANGES 16 /* number of ranges avail */
! 154:
! 155: /* sbus_ssel0..15: sbus slot select registers */
! 156: #define SBUS_SSEL_X 0x70 /* slot select pins range X */
! 157: #define SBUS_SSEL_X_SLOT1 0x00 /* sbus slot 1 */
! 158: #define SBUS_SSEL_X_SLOT2 0x10 /* sbus slot 2 */
! 159: #define SBUS_SSEL_X_SLOT3 0x20 /* sbus slot 3 */
! 160: #define SBUS_SSEL_X_SLOT4 0x30 /* sbus slot 4 */
! 161: #define SBUS_SSEL_X_SLOT5x 0x40 /* sbus slot 5? */
! 162: #define SBUS_SSEL_X_SLOT5 0x50 /* sbus slot 5 */
! 163: #define SBUS_SSEL_Y 0x07 /* slot select pins range X+1*/
! 164: #define SBUS_SSEL_Y_SLOT1 0x00 /* sbus slot 1 */
! 165: #define SBUS_SSEL_Y_SLOT2 0x01 /* sbus slot 2 */
! 166: #define SBUS_SSEL_Y_SLOT3 0x02 /* sbus slot 3 */
! 167: #define SBUS_SSEL_Y_SLOT4 0x03 /* sbus slot 4 */
! 168: #define SBUS_SSEL_Y_SLOT5x 0x04 /* sbus slot 5? */
! 169: #define SBUS_SSEL_Y_SLOT5 0x05 /* sbus slot 5 */
! 170:
! 171: /* viack_emu1..7: iack emulation registers */
! 172: /* bits contain d00-d07 from VMEbus interrupter */
! 173:
! 174: /* sbus_cap: sbus capability register */
! 175: #define SBUS_CAP_BURSTMASK 0xc0 /* dma burst size mask */
! 176: #define SBUS_CAP_BURST_64 0xc0 /* 64 byte burst */
! 177: #define SBUS_CAP_BURST_32 0x80 /* 32 byte burst */
! 178: #define SBUS_CAP_BURST_16 0x40 /* 16 byte burst */
! 179: #define SBUS_CAP_BURST_8 0x00 /* 8 byte burst */
! 180: #define SBUS_CAP_READSTOPMASK 0x30 /* master read stop point */
! 181: #define SBUS_CAP_READSTOP_64 0x30 /* stop at 64 byte boundary */
! 182: #define SBUS_CAP_READSTOP_32 0x20 /* stop at 32 byte boundary */
! 183: #define SBUS_CAP_READSTOP_16 0x10 /* stop at 16 byte boundary */
! 184: #define SBUS_CAP_READSTOP_8 0x00 /* stop at 8 byte boundary */
! 185: #define SBUS_CAP_BURSTDIS 0x08 /* disable sbus bursts */
! 186: #define SBUS_CAP_HIDDENARBDIS 0x04 /* disable sbus hidden arb */
! 187: #define SBUS_CAP_SPLITFLOW 0x02 /* disable flow through */
! 188:
! 189: /* sbus_retry_ctrl: sbus retry register */
! 190: /* clock cycles with no acknowledge */
! 191:
! 192: /* sbus_rerun_ctrl: sbus rerun limit register */
! 193: /* number of times to reruns to try on the bus */
! 194:
! 195: /* swpar: sbus write posting error address register */
! 196: /* virtual sbus transfer address that was ack'd with an error */
! 197:
! 198: /* slerr: sbus late error address register */
! 199: /* virtual sbus address that resulted in a late transfer */
! 200:
! 201: /* vme_base: VMEbus base address register */
! 202: #define VME_BASE_RMVBA 0xfe /* reg map base address */
! 203: #define VME_BASE_RMACCEN 0x01 /* reg remote access enable */
! 204:
! 205: /* vme_ext0..2: slave address extension registers */
! 206: /* extensions of A24 VMEbus address to 32bit sbus address (msb) */
! 207:
! 208: /* sbus_range0..2: slave range registers */
! 209: #define SBUS_RANGE_VSRCC 0xfff00000 /* slave range compare code */
! 210: #define SBUS_RANGE_VSAT 0x000ffe00 /* slave address translation */
! 211: #define SBUS_RANGE_A32DIS 0x00000004 /* disable A32 (enable A24) */
! 212: #define SBUS_RANGE_WPDIS 0x00000002 /* disable write posting */
! 213: #define SBUS_RANGE_DECDIS 0x00000001 /* disable encoding */
! 214:
! 215: /* ibox_addr: IBOX address register */
! 216: /* address within VME A16 space where the IBOX is accessed */
! 217:
! 218: /* ibox_ctrl: IBOX control register */
! 219: #define IBOX_CTRL_DIS 0x01 /* disable ibox */
! 220:
! 221: /* fmb_ctrl: force message broadcast control register */
! 222: #define FMB_CTRL_SELAM 0x80 /* supervisor/user access */
! 223: #define FMB_CTRL_DISCH1 0x40 /* disable channel 1 */
! 224: #define FMB_CTRL_DISCH2 0x20 /* disable channel 2 */
! 225: #define FMB_CTRL_SLOTID 0x1f /* slot id: 1-15 */
! 226:
! 227: /* vme_cap: global master capability register */
! 228: #define VME_CAP_NPRV 0x80 /* supervisor access */
! 229:
! 230: /* vmebus_handshake: VMEbus handshake configuration register */
! 231: #define VME_HANDSHAKE_DISSGLE 0x80 /* disable glitch filter */
! 232: #define VME_HANDSHAKE_DISASFAST 0x40 /* disable fast AS handshake */
! 233: #define VME_HANDSHAKE_DISDS 0x20 /* disable fast data strobe */
! 234:
! 235: /* vwpar: VMEbus write posting address register */
! 236: /* contains address ack'd with a BERR from the VME bus */
! 237:
! 238: /* dma_ctrl: dma control register */
! 239: #define DMA_CTRL_DMAEN 0x80 /* enable (start) dma */
! 240: #define DMA_CTRL_DMADIS 0x40 /* disable dma transaction */
! 241: #define DMA_CTRL_DMAHLT 0x20 /* stop dma transaction */
! 242: #define DMA_CTRL_DMARESU 0x10 /* resume dma transaction */
! 243:
! 244: /* dma_mode: dma mode register */
! 245: #define DMA_MODE_DMASB 0x80 /* single buffer mode */
! 246: #define DMA_MODE_DMANRTRY 0x40 /* error on retry */
! 247:
! 248: /* dma_stat: dma status register */
! 249: #define DMA_STAT_DMARUN 0x80 /* dma task is running */
! 250: #define DMA_STAT_DMAWT 0x40 /* dma task is halted */
! 251: #define DMA_STAT_DMANT 0x20 /* dma task successful */
! 252: #define DMA_STAT_ERRMASK 0x18 /* dma error mask */
! 253: #define DMA_STAT_ERR_SRC 0x00 /* error on source bus */
! 254: #define DMA_STAT_ERR_DST 0x08 /* error on destination bus */
! 255: #define DMA_STAT_ERR_NONE 0x10 /* no error termination */
! 256: #define DMA_STAT_ERR_NOERROR 0x18 /* no error termination */
! 257:
! 258: /* dma_src: dma source address register */
! 259: #define DMA_SRC_ADDR 0xfffffffc /* source address */
! 260: #define DMA_SRC_VME 0x00000002 /* 0=vme, 1=sbus */
! 261:
! 262: /* dma_dst: dma destination address register */
! 263: #define DMA_DST_ADDR 0xfffffffc /* destination address */
! 264: #define DMA_DST_VME 0x00000002 /* 0=vme, 1=sbus */
! 265:
! 266: /* dma_captl: dma capability/transfer length */
! 267: #define DMA_CAPTL_SCAPD_MASK 0xe0000000 /* src data capability */
! 268: #define DMA_CAPTL_SCAPD_D8 0x00000000 /* D8 slave */
! 269: #define DMA_CAPTL_SCAPD_D16 0x20000000 /* D16 slave */
! 270: #define DMA_CAPTL_SCAPD_D32 0x40000000 /* D32 slave */
! 271: #define DMA_CAPTL_SCAPD_BLT 0x60000000 /* BLT slave */
! 272: #define DMA_CAPTL_SCAPD_MBLT 0x80000000 /* MBLT slave */
! 273: #define DMA_CAPTL_SCAPA_MASK 0x1c000000 /* src addr capability */
! 274: #define DMA_CAPTL_SCAPA_A16 0x00000000 /* A16 slave */
! 275: #define DMA_CAPTL_SCAPA_A24 0x04000000 /* A24 slave */
! 276: #define DMA_CAPTL_SCAPA_A32 0x08000000 /* A32 slave */
! 277: #define DMA_CAPTL_DCAPD_MASK 0x03800000 /* dst data capability */
! 278:
! 279: /* mbox0..15: mailbox registers */
! 280: #define MBOX_SEM 0x80 /* semaphore bit */
! 281:
! 282: /* sem0..47: semaphore registers */
! 283: #define SEM_SEM 0x80 /* semaphore bit */
! 284:
! 285: /* gcsr: global control and status register */
! 286: #define GCSR_SETSYSFAIL 0x80 /* assert SYSFAIL* signal */
! 287: #define GCSR_ENSYSFAIL 0x40 /* enable SYSFAIL* output */
! 288: #define GCSR_SYSFAIL 0x20 /* SYSFAIL* input status */
! 289: #define GCSR_RESET 0x10 /* software reset */
! 290: #define GCSR_ACFAIL 0x08 /* ACFAIL input status */
! 291: #define GCSR_DISVDR 0x04 /* disable VME DTB drivers */
! 292: #define GCSR_ENSYSCON 0x02 /* enable system controller */
! 293:
! 294: /* reset_stat: reset status register */
! 295: #define RESET_STAT_SBUS_RESET 0x80 /* sbus has been reset */
! 296: #define RESET_STAT_VME_SYSRES 0x40 /* vmebus has been reset */
! 297: #define RESET_STAT_WDT_RESET 0x20 /* watchdog has triggered */
! 298: #define RESET_STAT_SYSRES_CALL 0x04 /* sysreset in mcsr0 set */
! 299: #define RESET_STAT_RESET_CALL 0x02 /* reset in mcsr0 set */
! 300: #define RESET_STAT_LOCRES_CALL 0x01 /* reset in ccsr set */
! 301:
! 302: /* *irq_map: interrupt request mapping registers */
! 303: #define IRQ_MAP_ENABLE 0x08 /* enable irq */
! 304: #define IRQ_MAP_INT_MASK 0x07 /* irq mapping mask */
! 305: #define IRQ_MAP_INT 0x00 /* NMI */
! 306: #define IRQ_MAP_SINT1 0x01 /* sbus pri 1 */
! 307: #define IRQ_MAP_SINT2 0x02 /* sbus pri 2 */
! 308: #define IRQ_MAP_SINT3 0x03 /* sbus pri 3 */
! 309: #define IRQ_MAP_SINT4 0x04 /* sbus pri 4 */
! 310: #define IRQ_MAP_SINT5 0x05 /* sbus pri 5 */
! 311: #define IRQ_MAP_SINT6 0x06 /* sbus pri 6 */
! 312: #define IRQ_MAP_SINT7 0x07 /* sbus pri 7 */
! 313:
! 314: /* mbox_stat: mailbox status interrupt status register */
! 315: /* 1 bit for each mailbox, 0 = interrupt pending, 1 = no interrupt pending */
! 316:
! 317: /* arb_ctrl: arbitration control register */
! 318: #define ARB_CTRL_MASK 0xc0 /* control mask */
! 319: #define ARB_CTRL_PRIORITY 0xc0 /* priority mode */
! 320: #define ARB_CTRL_ROBIN 0x40 /* round robin mode */
! 321: #define ARB_CTRL_PRIROBIN 0x80 /* priority round robin mode */
! 322:
! 323: /* req_ctrl: VMEbus request control register */
! 324: #define REQ_CTRL_FM 0x80 /* 0=fair,1=demand mode */
! 325: #define REQ_CTRL_RM_MASK 0x70 /* release mode mask */
! 326: #define REQ_CTRL_RM_ROR 0x30 /* release on request */
! 327: #define REQ_CTRL_RM_ROC 0x40 /* release on bus clear */
! 328: #define REQ_CTRL_RM_RAT 0x60 /* release after timeout */
! 329: #define REQ_CTRL_RM_RWD 0x70 /* release when done */
! 330: #define REQ_CTRL_REC 0x08 /* 0=begin,1=end of cycle */
! 331: #define REQ_CTRL_RL_MASK 0x06 /* request level mask */
! 332: #define REQ_CTRL_RL_BR3 0x06 /* br3 priority */
! 333: #define REQ_CTRL_RL_BR2 0x04 /* br2 priority */
! 334: #define REQ_CTRL_RL_BR1 0x02 /* br1 priority */
! 335: #define REQ_CTRL_RL_BR0 0x00 /* br0 priority */
! 336: #define REQ_CTRL_GLFI 0x01 /* enable bbsy glitch filter */
! 337:
! 338: /* bus_ctrl: VMEbus capture register */
! 339: #define BUS_CTRL_BCAP 0x80 /* request and keep bus */
! 340: #define BUS_CTRL_OWN 0x40 /* do we own the bus? */
! 341:
! 342: /* mcsr0: miscellaneous control and status register 0 */
! 343: #define MCSR0_ABORTSW 0x80 /* status of abort switch */
! 344: #define MCSR0_SCON 0x40 /* status of SCON input */
! 345: #define MCSR0_SYSRESET 0x20 /* assert SYSRESET* */
! 346: #define MCSR0_RESET 0x10 /* software reset fga5000 */
! 347: #define MCSR0_ENA_VME_TIMEOUT 0x08 /* enable VME timeout */
! 348: #define MCSR0_VME_TIMEOUT_MASK 0x06 /* VME transaction timeout */
! 349: #define MCSR0_VME_TIMEOUT_32 0x02 /* 32 usec */
! 350: #define MCSR0_VME_TIMEOUT_128 0x04 /* 128 usec */
! 351: #define MCSR0_VME_TIMEOUT_512 0x06 /* 512 usec */
! 352: #define MCSR0_SYSRESET_IN 0x01 /* enable SYSRESET input */
! 353:
! 354: /* mcsr1: miscellaneous control and status register 1 */
! 355: #define MCSR1_ENAWDT 0x80 /* enable watchdog timer */
! 356: #define MCSR1_TIMEOUT_MASK 0x70 /* watchdog timeout mask */
! 357: #define MCSR1_TIMEOUT_408MS 0x00 /* 408 msec */
! 358: #define MCSR1_TIMEOUT_168S 0x10 /* 1.68 sec */
! 359: #define MCSR1_TIMEOUT_67S 0x20 /* 6.7 sec */
! 360: #define MCSR1_TIMEOUT_268S 0x30 /* 26.8 sec */
! 361: #define MCSR1_TIMEOUT_1M48S 0x40 /* 1 min 48 sec */
! 362: #define MCSR1_TIMEOUT_7M9S 0x50 /* 7 min 9 sec */
! 363: #define MCSR1_TIMEOUT_28M38S 0x60 /* 28 min 38 sec */
! 364: #define MCSR1_TIMEOUT_1H54M 0x70 /* 1 hour 54 min */
! 365: #define MCSR1_IRQ_FREEZE 0x08 /* freeze irq map regs */
! 366:
! 367: /* wdt_restart: watchdog timer restart register */
! 368: /* any read/write resets the watchdog timer */
! 369:
! 370: /* intr_stat: interrupt status register */
! 371: #define INTR_STAT_ACFAIL 0x80000000 /* acfail pending */
! 372: #define INTR_STAT_SYSFAILASSERT 0x40000000 /* sysfail assert pending */
! 373: #define INTR_STAT_SYSFAILNEGATE 0x20000000 /* sysfail negate pending */
! 374: #define INTR_STAT_ABORT 0x10000000 /* abort pending */
! 375: #define INTR_STAT_ARBTIMEOUT 0x08000000 /* arbitration timeout */
! 376: #define INTR_STAT_MAILBOX 0x04000000 /* mailbox intr pending */
! 377: #define INTR_STAT_SBUS_WPERR 0x02000000 /* sbus wperr pending */
! 378: #define INTR_STAT_VME_WPERR 0x01000000 /* vme wperr pending */
! 379: #define INTR_STAT_DMATERM 0x00800000 /* dma finished */
! 380: #define INTR_STAT_WDT 0x00400000 /* watchdog half timeout */
! 381: #define INTR_STAT_SLERR 0x00200000 /* sbus late error pending */
! 382: #define INTR_STAT_IBOX 0x00100000 /* ibox pending */
! 383: #define INTR_STAT_FMB0 0x00080000 /* fmb channel 0 pending */
! 384: #define INTR_STAT_FMB1 0x00040000 /* fmb channel 1 pending */
! 385: #define INTR_STAT_VMEIRQ7 0x00000080 /* vme irq 7 pending */
! 386: #define INTR_STAT_VMEIRQ6 0x00000040 /* vme irq 6 pending */
! 387: #define INTR_STAT_VMEIRQ5 0x00000020 /* vme irq 5 pending */
! 388: #define INTR_STAT_VMEIRQ4 0x00000010 /* vme irq 4 pending */
! 389: #define INTR_STAT_VMEIRQ3 0x00000008 /* vme irq 3 pending */
! 390: #define INTR_STAT_VMEIRQ2 0x00000004 /* vme irq 2 pending */
! 391: #define INTR_STAT_VMEIRQ1 0x00000002 /* vme irq 1 pending */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to fgareg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / sparc / dev