Annotation of sys/arch/sparc/dev/daadioreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: daadioreg.h,v 1.2 2003/06/02 18:40:59 jason Exp $ */
2:
3: /*
4: * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
5: * All rights reserved.
6: *
7: * This software was developed by Jason L. Wright under contract with
8: * RTMX Incorporated (http://www.rtmx.com).
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: *
19: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
23: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
28: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29: * POSSIBILITY OF SUCH DAMAGE.
30: */
31:
32: /*
33: * Register definitions for Matrix Corporation MD-DAADIO VME
34: * digital/analog, analog/digitial, parallel i/o board.
35: * Definitions from "MD-DAADIO User's Manual" revision B.3
36: */
37:
38: struct daadioregs {
39: volatile u_int8_t _unused0[32]; /* reserved */
40: /* PIO module: 0x20-0x27 */
41: volatile u_int8_t pio_portb; /* port b */
42: volatile u_int8_t pio_porta; /* port a */
43: volatile u_int8_t pio_portd; /* port d */
44: volatile u_int8_t pio_portc; /* port c */
45: volatile u_int8_t pio_portf; /* port f */
46: volatile u_int8_t pio_porte; /* port e */
47: volatile u_int8_t _unused1[1]; /* reserved */
48: volatile u_int8_t pio_oc; /* output control */
49:
50: volatile u_int8_t _unused2[24]; /* reserved */
51:
52: /* DAC module: 0x40-0x4f */
53: volatile u_int16_t dac_channel[8]; /* dac channels 0-7 */
54:
55: volatile u_int8_t _unused3[16]; /* reserved */
56:
57: /* Miscellaneous: 0x60-0x69 */
58: volatile u_int8_t _unused4; /* reserved */
59: volatile u_int8_t gvrilr; /* gain value/irq level */
60: volatile u_int8_t _unused5; /* reserved */
61: volatile u_int8_t ier; /* irq enable (wo) */
62: volatile u_int8_t _unused6; /* reserved */
63: volatile u_int8_t pio_pattern; /* pio pattern */
64: volatile u_int8_t _unused7; /* reserved */
65: volatile u_int8_t sid; /* status/id */
66: volatile u_int8_t _unused8; /* reserved */
67: volatile u_int8_t isr; /* interrupt status */
68:
69: volatile u_int8_t _unused9[22]; /* reserved */
70:
71: /* ADC module: 0x80-0xff */
72: volatile u_int16_t adc12bit[32]; /* adc 12 bit channels 0-31 */
73: volatile u_int16_t adc8bit[32]; /* adc 8 bit channels 0-31 */
74: };
75:
76: /*
77: * The board occupies the space from 0 - 3ff (from some board configured
78: * offset). There are four register mappings (the last three are redundant
79: * mappings of the first)
80: */
81: struct daadioboard {
82: struct daadioregs regs0;
83: struct daadioregs regs1;
84: struct daadioregs regs2;
85: struct daadioregs regs3;
86: };
87:
88: /* gain value register/irq level register (gvr/ilr) */
89: #define ILR_TRIGGER 0x80 /* 0=internal,1=external */
90: #define ILR_IRQ_MASK 0x70 /* IRQ level */
91: #define ILR_IRQ_SHIFT 4 /* irq shift to/from lsbits */
92: #define ILR_ADC_GAINMASK 0x07 /* adc gain select bits */
93: #define ILR_ADC_GAIN1 0x00 /* 1x adc gain */
94: #define ILR_ADC_GAIN2 0x01 /* 2x adc gain */
95: #define ILR_ADC_GAIN4 0x02 /* 4x adc gain */
96: #define ILR_ADC_GAIN8 0x03 /* 8x adc gain */
97: #define ILR_ADC_GAIN16 0x04 /* 16x adc gain */
98:
99: /* interrupt enable register (ier): WRITE ONLY */
100: #define IER_MASK 0x07 /* interrupt bits */
101: #define IER_PIPELINE 0x04 /* adc pipeline empty */
102: #define IER_CONVERSION 0x02 /* adc conversion done */
103: #define IER_PIOEVENT 0x01 /* pio event triggered */
104:
105: /* interrupt status register (isr) */
106: #define ISR_MASK 0x07 /* interrupt bits */
107: #define ISR_PIPELINE 0x04 /* adc pipeline empty */
108: #define ISR_CONVERSION 0x02 /* adc conversion done */
109: #define ISR_PIOEVENT 0x01 /* pio event triggered */
110:
111: /* analog/digital data register */
112: #define ADC_IV 0x1000 /* invalid (out of range) */
113: #define ADC_PR 0x2000 /* pipeline empty */
114: #define ADC_DR 0x4000 /* data ready (valid) */
115: #define ADC_OW 0x8000 /* data overwritten */
116: #define ADC_DATAMASK 0x0fff /* the actual data */
117:
118: /* output control register (pio_oc) */
119: #define PIOC_OCA 0x01 /* enable port A output */
120: #define PIOC_OCB 0x02 /* enable port B output */
121: #define PIOC_OCC 0x03 /* enable port C output */
122: #define PIOC_OCD 0x04 /* enable port D output */
123: #define PIOC_OCE 0x05 /* enable port E output */
124: #define PIOC_OCF 0x06 /* enable port F output */
125:
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