Annotation of sys/arch/sparc/dev/cgsixreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cgsixreg.h,v 1.6 2003/06/02 23:27:54 millert Exp $ */
2: /* $NetBSD: cgsixreg.h,v 1.4 1996/02/27 22:09:31 thorpej Exp $ */
3:
4: /*
5: * Copyright (c) 2002 Jason L. Wright (jason@thought.net)
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: *
17: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
19: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
20: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
21: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
22: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
25: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
26: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27: * POSSIBILITY OF SUCH DAMAGE.
28: */
29: /*
30: * Copyright (c) 1993
31: * The Regents of the University of California. All rights reserved.
32: *
33: * This software was developed by the Computer Systems Engineering group
34: * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
35: * contributed to Berkeley.
36: *
37: * All advertising materials mentioning features or use of this software
38: * must display the following acknowledgement:
39: * This product includes software developed by the University of
40: * California, Lawrence Berkeley Laboratory.
41: *
42: * Redistribution and use in source and binary forms, with or without
43: * modification, are permitted provided that the following conditions
44: * are met:
45: * 1. Redistributions of source code must retain the above copyright
46: * notice, this list of conditions and the following disclaimer.
47: * 2. Redistributions in binary form must reproduce the above copyright
48: * notice, this list of conditions and the following disclaimer in the
49: * documentation and/or other materials provided with the distribution.
50: * 3. Neither the name of the University nor the names of its contributors
51: * may be used to endorse or promote products derived from this software
52: * without specific prior written permission.
53: *
54: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
55: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
56: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
57: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
58: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
59: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
60: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
61: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
62: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
63: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64: * SUCH DAMAGE.
65: *
66: * @(#)cgsixreg.h 8.4 (Berkeley) 1/21/94
67: */
68:
69: /*
70: * CG6 display registers.
71: *
72: * The cg6 is a complicated beastie. We have been unable to extract any
73: * documentation and most of the following are guesses based on a limited
74: * amount of reverse engineering.
75: *
76: * A cg6 is composed of numerous groups of control registers, all with TLAs:
77: * FBC - frame buffer control?
78: * FHC - fbc hardware configuration / control? register (32 bits)
79: * DHC - ???
80: * TEC - transform engine control?
81: * THC - TEC Hardware Configuration
82: * ROM - a 64Kbyte ROM with who knows what in it.
83: * colormap - see below
84: * frame buffer memory (video RAM)
85: * possible other stuff
86: *
87: * Like the cg3, the cg6 uses a Brooktree Video DAC (see btreg.h).
88: *
89: * Various revisions of the cgsix have various hardware bugs. So far,
90: * we have only seen rev 1 & 2.
91: */
92:
93: /* offsets */
94: #define CGSIX_ROM_OFFSET 0x000000
95: #define CGSIX_BT_OFFSET 0x200000
96: #define CGSIX_BT_SIZE (sizeof(u_int32_t) * 4)
97: #define CGSIX_DHC_OFFSET 0x240000
98: #define CGSIX_ALT_OFFSET 0x280000
99: #define CGSIX_FHC_OFFSET 0x300000
100: #define CGSIX_FHC_SIZE (sizeof(u_int32_t) * 1)
101: #define CGSIX_THC_OFFSET 0x301000
102: #define CGSIX_THC_SIZE (sizeof(u_int32_t) * 640)
103: #define CGSIX_FBC_OFFSET 0x700000
104: #define CGSIX_FBC_SIZE 0x1000
105: #define CGSIX_TEC_OFFSET 0x701000
106: #define CGSIX_TEC_SIZE (sizeof(u_int32_t) * 3)
107: #define CGSIX_VID_OFFSET 0x800000
108: #define CGSIX_VID_SIZE (1024 * 1024)
109:
110: #define CG6_FHC 0x0 /* fhc register */
111:
112: /* bits in FHC register */
113: #define FHC_FBID_MASK 0xff000000 /* frame buffer id */
114: #define FHC_FBID_SHIFT 24
115: #define FHC_REV_MASK 0x00f00000 /* revision */
116: #define FHC_REV_SHIFT 20
117: #define FHC_FROP_DISABLE 0x00080000 /* disable fast rasterop */
118: #define FHC_ROW_DISABLE 0x00040000 /* ??? */
119: #define FHC_SRC_DISABLE 0x00020000 /* ??? */
120: #define FHC_DST_DISABLE 0x00010000 /* disable dst cache */
121: #define FHC_RESET 0x00008000 /* ??? */
122: #define FHC_LEBO 0x00002000 /* set little endian order */
123: #define FHC_RES_MASK 0x00001800 /* resolution: */
124: #define FHC_RES_1024 0x00000000 /* 1024x768 */
125: #define FHC_RES_1152 0x00000800 /* 1152x900 */
126: #define FHC_RES_1280 0x00001000 /* 1280x1024 */
127: #define FHC_RES_1600 0x00001800 /* 1600x1200 */
128: #define FHC_CPU_MASK 0x00000600 /* cpu type: */
129: #define FHC_CPU_SPARC 0x00000000 /* sparc */
130: #define FHC_CPU_68020 0x00000200 /* 68020 */
131: #define FHC_CPU_386 0x00000400 /* i386 */
132: #define FHC_TEST 0x00000100 /* test window */
133: #define FHC_TESTX_MASK 0x000000f0 /* test window X */
134: #define FHC_TESTX_SHIFT 4
135: #define FHC_TESTY_MASK 0x0000000f /* test window Y */
136: #define FHC_TESTY_SHIFT 0
137:
138: struct cgsix_fbc {
139: u_int32_t fbc_xxx0[1];
140: u_int32_t fbc_mode; /* mode setting */
141: u_int32_t fbc_clip; /* ??? */
142: u_int32_t fbc_xxx1[1];
143: u_int32_t fbc_s; /* global status */
144: u_int32_t fbc_draw; /* drawing pipeline status */
145: u_int32_t fbc_blit; /* blitter status */
146: u_int32_t fbc_xxx2[25];
147: u_int32_t fbc_x0; /* blitter, src llx */
148: u_int32_t fbc_y0; /* blitter, src lly */
149: u_int32_t fbc_xxx3[2];
150: u_int32_t fbc_x1; /* blitter, src urx */
151: u_int32_t fbc_y1; /* blitter, src ury */
152: u_int32_t fbc_xxx4[2];
153: u_int32_t fbc_x2; /* blitter, dst llx */
154: u_int32_t fbc_y2; /* blitter, dst lly */
155: u_int32_t fbc_xxx5[2];
156: u_int32_t fbc_x3; /* blitter, dst urx */
157: u_int32_t fbc_y3; /* blitter, dst ury */
158: u_int32_t fbc_xxx6[2];
159: u_int32_t fbc_offx; /* x offset for drawing */
160: u_int32_t fbc_offy; /* y offset for drawing */
161: u_int32_t fbc_xxx7[6];
162: u_int32_t fbc_clipminx; /* clip rectangle llx */
163: u_int32_t fbc_clipminy; /* clip rectangle lly */
164: u_int32_t fbc_xxx8[2];
165: u_int32_t fbc_clipmaxx; /* clip rectangle urx */
166: u_int32_t fbc_clipmaxy; /* clip rectangle ury */
167: u_int32_t fbc_xxx9[2];
168: u_int32_t fbc_fg; /* fg value for rop */
169: u_int32_t fbc_xxx10[1];
170: u_int32_t fbc_alu; /* operation */
171: u_int32_t fbc_xxx11[509];
172: u_int32_t fbc_arectx; /* rectangle drawing, x coord */
173: u_int32_t fbc_arecty; /* rectangle drawing, y coord */
174: };
175:
176: #define FBC_MODE_MASK ( \
177: 0x00300000 /* GX_BLIT_ALL */ \
178: | 0x00060000 /* GX_MODE_ALL */ \
179: | 0x00018000 /* GX_DRAW_ALL */ \
180: | 0x00006000 /* GX_BWRITE0_ALL */ \
181: | 0x00001800 /* GX_BWRITE1_ALL */ \
182: | 0x00000600 /* GX_BREAD_ALL */ \
183: | 0x00000180 /* GX_BDISP_ALL */ \
184: )
185:
186: #define FBC_MODE_VAL ( \
187: 0x00200000 /* GX_BLIT_SRC */ \
188: | 0x00020000 /* GX_MODE_COLOR8 */ \
189: | 0x00008000 /* GX_DRAW_RENDER */ \
190: | 0x00002000 /* GX_BWRITE0_ENABLE */ \
191: | 0x00001000 /* GX_BWRITE1_DISABLE */ \
192: | 0x00000200 /* GX_BREAD_0 */ \
193: | 0x00000080 /* GX_BDISP_0 */ \
194: )
195:
196: #define FBC_S_GXINPROGRESS 0x10000000 /* drawing in progress */
197:
198: #define FBC_BLIT_UNKNOWN 0x80000000 /* ??? */
199: #define FBC_BLIT_GXFULL 0x20000000 /* queue is full */
200:
201: #define FBC_DRAW_UNKNOWN 0x80000000 /* ??? */
202: #define FBC_DRAW_GXFULL 0x20000000
203:
204: /* Value for the alu register for screen-to-screen copies */
205: #define FBC_ALU_COPY ( \
206: 0x80000000 /* GX_PLANE_ONES (ignore planemask register) */ \
207: | 0x20000000 /* GX_PIXEL_ONES (ignore pixelmask register) */ \
208: | 0x00800000 /* GX_ATTR_SUPP (function unknown) */ \
209: | 0x00000000 /* GX_RAST_BOOL (function unknown) */ \
210: | 0x00000000 /* GX_PLOT_PLOT (function unknown) */ \
211: | 0x08000000 /* GX_PATTERN_ONES (ignore pattern) */ \
212: | 0x01000000 /* GX_POLYG_OVERLAP (unsure - handle overlap?) */ \
213: | 0x0000cccc /* ALU = src */ \
214: )
215:
216: /* Value for the alu register for region fills */
217: #define FBC_ALU_FILL ( \
218: 0x80000000 /* GX_PLANE_ONES (ignore planemask register) */ \
219: | 0x20000000 /* GX_PIXEL_ONES (ignore pixelmask register) */ \
220: | 0x00800000 /* GX_ATTR_SUPP (function unknown) */ \
221: | 0x00000000 /* GX_RAST_BOOL (function unknown) */ \
222: | 0x00000000 /* GX_PLOT_PLOT (function unknown) */ \
223: | 0x08000000 /* GX_PATTERN_ONES (ignore pattern) */ \
224: | 0x01000000 /* GX_POLYG_OVERLAP (unsure - handle overlap?) */ \
225: | 0x0000ff00 /* ALU = fg color */ \
226: )
227:
228: /* Value for the alu register for toggling an area */
229: #define FBC_ALU_FLIP ( \
230: 0x80000000 /* GX_PLANE_ONES (ignore planemask register) */ \
231: | 0x20000000 /* GX_PIXEL_ONES (ignore pixelmask register) */ \
232: | 0x00800000 /* GX_ATTR_SUPP (function unknown) */ \
233: | 0x00000000 /* GX_RAST_BOOL (function unknown) */ \
234: | 0x00000000 /* GX_PLOT_PLOT (function unknown) */ \
235: | 0x08000000 /* GX_PATTERN_ONES (ignore pattern) */ \
236: | 0x01000000 /* GX_POLYG_OVERLAP (unsure - handle overlap?) */ \
237: | 0x00005555 /* ALU = ~dst */ \
238: )
239:
240: /*
241: * The layout of the THC.
242: */
243: struct cgsix_thc {
244: u_int32_t thc_xxx0[512]; /* ??? */
245: u_int32_t thc_hsync1; /* horizontal sync timing */
246: u_int32_t thc_hsync2; /* more hsync timing */
247: u_int32_t thc_hsync3; /* yet more hsync timing */
248: u_int32_t thc_vsync1; /* vertical sync timing */
249: u_int32_t thc_vsync2; /* only two of these */
250: u_int32_t thc_refresh; /* refresh counter */
251: u_int32_t thc_misc; /* miscellaneous control & status */
252: u_int32_t thc_xxx1[56]; /* ??? */
253: u_int32_t thc_cursxy; /* cursor x,y position (16 bits each) */
254: u_int32_t thc_cursmask[32]; /* cursor mask bits */
255: u_int32_t thc_cursbits[32]; /* what to show where mask enabled */
256: };
257:
258: /* cursor x/y position for 'off' */
259: #define THC_CURSOFF ((65536-32) | ((65536-32) << 16))
260:
261: #define THC_MISC_REV_M 0x000f0000 /* chip revision */
262: #define THC_MISC_REV_S 16
263: #define THC_MISC_RESET 0x00001000 /* reset */
264: #define THC_MISC_VIDEN 0x00000400 /* video enable */
265: #define THC_MISC_SYNC 0x00000200 /* not sure what ... */
266: #define THC_MISC_VSYNC 0x00000100 /* ... these really are */
267: #define THC_MISC_SYNCEN 0x00000080 /* sync enable */
268: #define THC_MISC_CURSRES 0x00000040 /* cursor resolution */
269: #define THC_MISC_INTEN 0x00000020 /* v.retrace intr enable */
270: #define THC_MISC_INTR 0x00000010 /* intr pending/ack */
271: #define THC_MISC_CYCLS 0x0000000f /* cycles before transfer */
272:
273: /*
274: * Partial description of TEC (needed to get around FHC rev 1 bugs).
275: */
276: struct cgsix_tec_xxx {
277: u_int32_t tec_mv; /* matrix stuff */
278: u_int32_t tec_clip; /* clipping stuff */
279: u_int32_t tec_vdc; /* ??? */
280: };
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