Annotation of sys/arch/sparc/dev/bereg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: bereg.h,v 1.12 2003/06/02 18:40:59 jason Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 1998 Theo de Raadt and Jason L. Wright.
! 5: * All rights reserved.
! 6: *
! 7: * Redistribution and use in source and binary forms, with or without
! 8: * modification, are permitted provided that the following conditions
! 9: * are met:
! 10: * 1. Redistributions of source code must retain the above copyright
! 11: * notice, this list of conditions and the following disclaimer.
! 12: * 2. Redistributions in binary form must reproduce the above copyright
! 13: * notice, this list of conditions and the following disclaimer in the
! 14: * documentation and/or other materials provided with the distribution.
! 15: *
! 16: * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
! 17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 19: * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! 20: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 21: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 22: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 23: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 24: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 25: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 26: */
! 27:
! 28: /*
! 29: * BE Global registers
! 30: */
! 31: struct be_bregs {
! 32: volatile u_int32_t xif_cfg; /* XIF config */
! 33: volatile u_int32_t _unused[63]; /* reserved */
! 34: volatile u_int32_t stat; /* status, clear on read */
! 35: volatile u_int32_t imask; /* interrupt mask */
! 36: volatile u_int32_t _unused2[64]; /* reserved */
! 37: volatile u_int32_t tx_swreset; /* tx software reset */
! 38: volatile u_int32_t tx_cfg; /* tx config */
! 39: volatile u_int32_t ipkt_gap1; /* inter-packet gap 1 */
! 40: volatile u_int32_t ipkt_gap2; /* inter-packet gap 2 */
! 41: volatile u_int32_t attempt_limit; /* tx attempt limit */
! 42: volatile u_int32_t stime; /* tx slot time */
! 43: volatile u_int32_t preamble_len; /* size of tx preamble */
! 44: volatile u_int32_t preamble_pattern; /* pattern for tx preamble */
! 45: volatile u_int32_t tx_sframe_delim; /* tx delimiter */
! 46: volatile u_int32_t jsize; /* jam length */
! 47: volatile u_int32_t tx_pkt_max; /* tx max pkt size */
! 48: volatile u_int32_t tx_pkt_min; /* tx min pkt size */
! 49: volatile u_int32_t peak_attempt; /* count of tx peak attempts */
! 50: volatile u_int32_t dt_ctr; /* tx defer timer */
! 51: volatile u_int32_t nc_ctr; /* tx normal collision cntr */
! 52: volatile u_int32_t fc_ctr; /* tx first-collision cntr */
! 53: volatile u_int32_t ex_ctr; /* tx excess-collision cntr */
! 54: volatile u_int32_t lt_ctr; /* tx late-collision cntr */
! 55: volatile u_int32_t rand_seed; /* tx random number seed */
! 56: volatile u_int32_t tx_smachine; /* tx state machine */
! 57: volatile u_int32_t _unused3[44]; /* reserved */
! 58: volatile u_int32_t rx_swreset; /* rx software reset */
! 59: volatile u_int32_t rx_cfg; /* rx config register */
! 60: volatile u_int32_t rx_pkt_max; /* rx max pkt size */
! 61: volatile u_int32_t rx_pkt_min; /* rx min pkt size */
! 62: volatile u_int32_t mac_addr2; /* ethernet address 2 (MSB) */
! 63: volatile u_int32_t mac_addr1; /* ethernet address 1 */
! 64: volatile u_int32_t mac_addr0; /* ethernet address 0 (LSB) */
! 65: volatile u_int32_t fr_ctr; /* rx frame receive cntr */
! 66: volatile u_int32_t gle_ctr; /* rx giant-len error cntr */
! 67: volatile u_int32_t unale_ctr; /* rx unaligned error cntr */
! 68: volatile u_int32_t rcrce_ctr; /* rx CRC error cntr */
! 69: volatile u_int32_t rx_smachine; /* rx state machine */
! 70: volatile u_int32_t rx_cvalid; /* rx code violation */
! 71: volatile u_int32_t _unused4; /* reserved */
! 72: volatile u_int32_t htable3; /* hash table 3 */
! 73: volatile u_int32_t htable2; /* hash table 2 */
! 74: volatile u_int32_t htable1; /* hash table 1 */
! 75: volatile u_int32_t htable0; /* hash table 0 */
! 76: volatile u_int32_t afilter2; /* address filter 2 */
! 77: volatile u_int32_t afilter1; /* address filter 1 */
! 78: volatile u_int32_t afilter0; /* address filter 0 */
! 79: volatile u_int32_t afilter_mask; /* address filter mask */
! 80: };
! 81:
! 82: /* be_bregs.xif_cfg: XIF config. */
! 83: #define BE_BR_XCFG_ODENABLE 0x00000001 /* output driver enable */
! 84: #define BE_BR_XCFG_RESV 0x00000002 /* reserved, write as 1 */
! 85: #define BE_BR_XCFG_MLBACK 0x00000004 /* loopback-mode mii enable */
! 86: #define BE_BR_XCFG_SMODE 0x00000008 /* enable serial mode */
! 87:
! 88: /* be_bregs.stat: status, clear on read. */
! 89: #define BE_BR_STAT_GOTFRAME 0x00000001 /* received a frame */
! 90: #define BE_BR_STAT_RCNTEXP 0x00000002 /* rx frame cntr expired */
! 91: #define BE_BR_STAT_ACNTEXP 0x00000004 /* align-error cntr expired */
! 92: #define BE_BR_STAT_CCNTEXP 0x00000008 /* crc-error cntr expired */
! 93: #define BE_BR_STAT_LCNTEXP 0x00000010 /* length-error cntr expired */
! 94: #define BE_BR_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */
! 95: #define BE_BR_STAT_CVCNTEXP 0x00000040 /* code-violation cntr exprd */
! 96: #define BE_BR_STAT_SENTFRAME 0x00000100 /* transmitted a frame */
! 97: #define BE_BR_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */
! 98: #define BE_BR_STAT_MAXPKTERR 0x00000400 /* max-packet size error */
! 99: #define BE_BR_STAT_NCNTEXP 0x00000800 /* normal-collision cntr exp */
! 100: #define BE_BR_STAT_ECNTEXP 0x00001000 /* excess-collision cntr exp */
! 101: #define BE_BR_STAT_LCCNTEXP 0x00002000 /* late-collision cntr exp */
! 102: #define BE_BR_STAT_FCNTEXP 0x00004000 /* first-collision cntr exp */
! 103: #define BE_BR_STAT_DTIMEXP 0x00008000 /* defer-timer expired */
! 104:
! 105: #define BE_BR_STAT_BITS "\20\1RX\2RCNT\3ACNT\4CCNT\5LCNT\6RFIFO\7CVCNT\11TX\12TFIFO\13TMAXPKT\14NCNT\15ECNT\16LCCNT\17ECNT\20DTIME"
! 106:
! 107: /* be_bregs.imask: interrupt mask. */
! 108: #define BE_BR_IMASK_GOTFRAME 0x00000001 /* received a frame */
! 109: #define BE_BR_IMASK_RCNTEXP 0x00000002 /* rx frame cntr expired */
! 110: #define BE_BR_IMASK_ACNTEXP 0x00000004 /* align-error cntr expired */
! 111: #define BE_BR_IMASK_CCNTEXP 0x00000008 /* crc-error cntr expired */
! 112: #define BE_BR_IMASK_LCNTEXP 0x00000010 /* length-error cntr expired */
! 113: #define BE_BR_IMASK_RFIFOVF 0x00000020 /* rx fifo overflow */
! 114: #define BE_BR_IMASK_CVCNTEXP 0x00000040 /* code-violation cntr exprd */
! 115: #define BE_BR_IMASK_SENTFRAME 0x00000100 /* transmitted a frame */
! 116: #define BE_BR_IMASK_TFIFO_UND 0x00000200 /* tx fifo underrun */
! 117: #define BE_BR_IMASK_MAXPKTERR 0x00000400 /* max-packet size error */
! 118: #define BE_BR_IMASK_NCNTEXP 0x00000800 /* normal-collision cntr exp */
! 119: #define BE_BR_IMASK_ECNTEXP 0x00001000 /* excess-collision cntr exp */
! 120: #define BE_BR_IMASK_LCCNTEXP 0x00002000 /* late-collision cntr exp */
! 121: #define BE_BR_IMASK_FCNTEXP 0x00004000 /* first-collision cntr exp */
! 122: #define BE_BR_IMASK_DTIMEXP 0x00008000 /* defer-timer expired */
! 123:
! 124: /* be_bregs.tx_cfg: tx config. */
! 125: #define BE_BR_TXCFG_ENABLE 0x00000001 /* enable the transmitter */
! 126: #define BE_BR_TXCFG_FIFO 0x00000010 /* default tx fthresh */
! 127: #define BE_BR_TXCFG_SMODE 0x00000020 /* enable slow transmit mode */
! 128: #define BE_BR_TXCFG_CIGN 0x00000040 /* ignore tx collisions */
! 129: #define BE_BR_TXCFG_FCSOFF 0x00000080 /* do not emit fcs */
! 130: #define BE_BR_TXCFG_DBACKOFF 0x00000100 /* disable backoff */
! 131: #define BE_BR_TXCFG_FULLDPLX 0x00000200 /* enable full-duplex */
! 132:
! 133: /* be_bregs.rx_cfg: rx config. */
! 134: #define BE_BR_RXCFG_ENABLE 0x00000001 /* enable the receiver */
! 135: #define BE_BR_RXCFG_FIFO 0x0000000e /* default rx fthresh */
! 136: #define BE_BR_RXCFG_PSTRIP 0x00000020 /* pad byte strip enable */
! 137: #define BE_BR_RXCFG_PMISC 0x00000040 /* enable promiscous mode */
! 138: #define BE_BR_RXCFG_DERR 0x00000080 /* disable error checking */
! 139: #define BE_BR_RXCFG_DCRCS 0x00000100 /* disable crc stripping */
! 140: #define BE_BR_RXCFG_ME 0x00000200 /* receive packets for me */
! 141: #define BE_BR_RXCFG_PGRP 0x00000400 /* enable promisc group mode */
! 142: #define BE_BR_RXCFG_HENABLE 0x00000800 /* enable hash filter */
! 143: #define BE_BR_RXCFG_AENABLE 0x00001000 /* enable address filter */
! 144:
! 145: /*
! 146: * BE Channel registers
! 147: */
! 148: struct be_cregs {
! 149: volatile u_int32_t ctrl; /* control */
! 150: volatile u_int32_t stat; /* status */
! 151: volatile u_int32_t rxds; /* rx descriptor ring ptr */
! 152: volatile u_int32_t txds; /* tx descriptor ring ptr */
! 153: volatile u_int32_t rimask; /* rx interrupt mask */
! 154: volatile u_int32_t timask; /* tx interrupt mask */
! 155: volatile u_int32_t qmask; /* qec error interrupt mask */
! 156: volatile u_int32_t bmask; /* be error interrupt mask */
! 157: volatile u_int32_t rxwbufptr; /* local memory rx write ptr */
! 158: volatile u_int32_t rxrbufptr; /* local memory rx read ptr */
! 159: volatile u_int32_t txwbufptr; /* local memory tx write ptr */
! 160: volatile u_int32_t txrbufptr; /* local memory tx read ptr */
! 161: volatile u_int32_t ccnt; /* collision counter */
! 162: };
! 163:
! 164: /* be_cregs.ctrl: control. */
! 165: #define BE_CR_CTRL_TWAKEUP 0x00000001 /* tx dma wakeup */
! 166:
! 167: /* be_cregs.stat: status. */
! 168: #define BE_CR_STAT_BERROR 0x80000000 /* be error */
! 169: #define BE_CR_STAT_TXIRQ 0x00200000 /* tx interrupt */
! 170: #define BE_CR_STAT_TXDERR 0x00080000 /* tx descriptor is bad */
! 171: #define BE_CR_STAT_TXLERR 0x00040000 /* tx late error */
! 172: #define BE_CR_STAT_TXPERR 0x00020000 /* tx parity error */
! 173: #define BE_CR_STAT_TXSERR 0x00010000 /* tx sbus error ack */
! 174: #define BE_CR_STAT_RXIRQ 0x00000020 /* rx interrupt */
! 175: #define BE_CR_STAT_RXDROP 0x00000010 /* rx packet dropped */
! 176: #define BE_CR_STAT_RXSMALL 0x00000008 /* rx buffer too small */
! 177: #define BE_CR_STAT_RXLERR 0x00000004 /* rx late error */
! 178: #define BE_CR_STAT_RXPERR 0x00000002 /* rx parity error */
! 179: #define BE_CR_STAT_RXSERR 0x00000001 /* rx sbus error ack */
! 180:
! 181: /*
! 182: * All bits except rxirq/txirq
! 183: */
! 184: #define BE_CR_STAT_ERRORS \
! 185: (BE_CR_STAT_BERROR | \
! 186: BE_CR_STAT_TXDERR | BE_CR_STAT_TXLERR | \
! 187: BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR | \
! 188: BE_CR_STAT_RXDROP | BE_CR_STAT_RXSMALL | \
! 189: BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | \
! 190: BE_CR_STAT_RXSERR)
! 191:
! 192: #define BE_CR_STAT_BITS \
! 193: "\20\1RXS\2RXP\3RXL\4RXSMALL\5RXDROP\6RX\21TXS\22TXP\23TXL\24TXD\26TX\40BE"
! 194:
! 195: /* be_cregs.qmask: qec error interrupt mask. */
! 196: #define BE_CR_QMASK_TXDERR 0x00080000 /* tx descriptor is bad */
! 197: #define BE_CR_QMASK_TXLERR 0x00040000 /* tx late error */
! 198: #define BE_CR_QMASK_TXPERR 0x00020000 /* tx parity error */
! 199: #define BE_CR_QMASK_TXSERR 0x00010000 /* tx sbus error ack */
! 200: #define BE_CR_QMASK_RXDROP 0x00000010 /* rx packet dropped */
! 201: #define BE_CR_QMASK_RXSMALL 0x00000008 /* rx buffer too small */
! 202: #define BE_CR_QMASK_RXLERR 0x00000004 /* rx late error */
! 203: #define BE_CR_QMASK_RXPERR 0x00000002 /* rx parity error */
! 204: #define BE_CR_QMASK_RXSERR 0x00000001 /* rx sbus error ack */
! 205:
! 206: /*
! 207: * BE Transceiver registers
! 208: */
! 209: struct be_tregs {
! 210: volatile u_int32_t tcvr_pal; /* transceiver pal */
! 211: volatile u_int32_t mgmt_pal; /* management pal */
! 212: };
! 213:
! 214: /* be_tregs.tcvr_pal: transceiver pal */
! 215: #define TCVR_PAL_SERIAL 0x00000001 /* serial mode enable */
! 216: #define TCVR_PAL_EXTLBACK 0x00000002 /* external loopback */
! 217: #define TCVR_PAL_MSENSE 0x00000004 /* media sense */
! 218: #define TCVR_PAL_LTENABLE 0x00000008 /* link test enable */
! 219: #define TCVR_PAL_LTSTATUS 0x00000010 /* link test status: p1 only */
! 220:
! 221: /* be_tregs.mgmt_pal: management pal */
! 222: #define MGMT_PAL_DCLOCK 0x00000001 /* data clock strobe */
! 223: #define MGMT_PAL_OENAB 0x00000002 /* output enable */
! 224: #define MGMT_PAL_MDIO 0x00000004 /* MDIO data/attached */
! 225: #define MGMT_PAL_EXT_MDIO MGMT_PAL_MDIO /* external mdio */
! 226: #define MGMT_PAL_TIMEO 0x00000008 /* tx enable timeout error */
! 227: #define MGMT_PAL_INT_MDIO MGMT_PAL_TIMEO /* internal mdio */
! 228:
! 229: /*
! 230: * BE receive descriptor
! 231: */
! 232: struct be_rxd {
! 233: volatile u_int32_t rx_flags; /* rx descriptor flags */
! 234: volatile u_int32_t rx_addr; /* rx buffer address */
! 235: };
! 236:
! 237: #define BE_RXD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */
! 238: #define BE_RXD_UPDATE 0x10000000 /* being updated? */
! 239: #define BE_RXD_LENGTH 0x00001fff /* packet length */
! 240:
! 241: /*
! 242: * BE transmit descriptor
! 243: */
! 244: struct be_txd {
! 245: volatile u_int32_t tx_flags; /* tx descriptor flags */
! 246: volatile u_int32_t tx_addr; /* tx buffer address */
! 247: };
! 248:
! 249: #define BE_TXD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */
! 250: #define BE_TXD_SOP 0x40000000 /* start of packet marker */
! 251: #define BE_TXD_EOP 0x20000000 /* end of packet marker */
! 252: #define BE_TXD_UPDATE 0x10000000 /* being updated? */
! 253: #define BE_TXD_LENGTH 0x00001fff /* packet length */
! 254:
! 255: /* Buffer and Ring sizes: fixed ring size */
! 256: #define BE_TX_RING_MAXSIZE 256 /* maximum tx ring size */
! 257: #define BE_RX_RING_MAXSIZE 256 /* maximum rx ring size */
! 258: #define BE_TX_RING_SIZE 32 /* power of 2, <= MAXSIZE */
! 259: #define BE_RX_RING_SIZE 32 /* power of 2, <= MAXSIZE */
! 260: #define BE_PKT_BUF_SZ 2048
! 261: #define BE_TX_HIGH_WATER 27 /* enable tx interrupt */
! 262: #define BE_TX_LOW_WATER 5 /* disable tx interrupt */
! 263:
! 264: #define BE_TX_RING_MAXMASK (BE_TX_RING_MAXSIZE-1)
! 265: #define BE_RX_RING_MAXMASK (BE_RX_RING_MAXSIZE-1)
! 266: #define BE_TX_RING_MASK (BE_TX_RING_SIZE-1)
! 267: #define BE_RX_RING_MASK (BE_RX_RING_SIZE-1)
! 268:
! 269: /*
! 270: * BE descriptor rings
! 271: */
! 272: struct be_desc {
! 273: struct be_rxd be_rxd[BE_RX_RING_MAXSIZE];
! 274: struct be_txd be_txd[BE_TX_RING_MAXSIZE];
! 275: };
! 276:
! 277: /*
! 278: * BE packet buffers
! 279: */
! 280: struct be_bufs {
! 281: char rx_buf[BE_RX_RING_SIZE][BE_PKT_BUF_SZ];
! 282: char tx_buf[BE_TX_RING_SIZE][BE_PKT_BUF_SZ];
! 283: };
! 284:
! 285: #define MC_POLY_BE 0x04c11db7UL /* mcast crc, big endian */
! 286: #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */
! 287:
! 288: /* PHY addresses */
! 289: #define BE_PHY_EXTERNAL 0
! 290: #define BE_PHY_INTERNAL 1
! 291:
! 292: /* Transceiver types */
! 293: #define BE_TCVR_NONE 0
! 294: #define BE_TCVR_INTERNAL 1
! 295: #define BE_TCVR_EXTERNAL 2
! 296:
! 297: #define BE_TCVR_READ_INVALID 0xff000000
! 298:
! 299: #define BE_NEGOTIATE_MAXTICKS 16
! 300:
! 301: #define PHY_BMCR 0x00 /* Basic Mode Control Register */
! 302: #define PHY_BMSR 0x01 /* Basic Mode Status Register */
! 303:
! 304: /*
! 305: * Basic Mode Control Register (BMCR)
! 306: */
! 307: #define PHY_BMCR_RESET 0x8000 /* Software reset */
! 308: #define PHY_BMCR_LOOPBACK 0x4000 /* Lookback enable */
! 309: #define PHY_BMCR_SPEED 0x2000 /* 1=100Mb, 0=10Mb */
! 310: #define PHY_BMCR_ANE 0x1000 /* Auto-Negiation enable */
! 311: #define PHY_BMCR_PDOWN 0x0800 /* power down the chip */
! 312: #define PHY_BMCR_ISOLATE 0x0400 /* Isolate the chip */
! 313: #define PHY_BMCR_RAN 0x0200 /* Restart autonegotiation */
! 314: #define PHY_BMCR_DUPLEX 0x0100 /* 1=full, 0=half */
! 315: #define PHY_BMCR_COLLISONTEST 0x0080 /* Create collisions on TX */
! 316:
! 317: /*
! 318: * Basic Mode Status Register (BMSR)
! 319: */
! 320: #define PHY_BMSR_100BASET4 0x8000 /* 100BaseT4 capable? */
! 321: #define PHY_BMSR_100BASETX_FULL 0x4000 /* 100BaseTX full duplex cap? */
! 322: #define PHY_BMSR_100BASETX_HALF 0x2000 /* 100BaseTX half duplex cap? */
! 323: #define PHY_BMSR_10BASET_FULL 0x1000 /* 10BaseT full duplex cap? */
! 324: #define PHY_BMSR_10BASET_HALF 0x0800 /* 10BaseT half duplex cap? */
! 325: #define PHY_BMSR_ANCOMPLETE 0x0020 /* auto-negotiation complete? */
! 326: #define PHY_BMSR_REMOTEFAULT 0x0010 /* Fault condition seen? */
! 327: #define PHY_BMSR_ANC 0x0008 /* Can auto-negotiate? */
! 328: #define PHY_BMSR_LINKSTATUS 0x0004 /* Link established? */
! 329: #define PHY_BMSR_JABBER 0x0002 /* Jabber detected? */
! 330: #define PHY_BMSR_EXTENDED 0x0001 /* Extended registers? */
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