Annotation of sys/arch/solbourne/include/kap.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: kap.h,v 1.2 2006/04/15 17:35:48 miod Exp $ */
! 2: /*
! 3: * Copyright (c) 2005, Miodrag Vallat
! 4: *
! 5: * Redistribution and use in source and binary forms, with or without
! 6: * modification, are permitted provided that the following conditions
! 7: * are met:
! 8: * 1. Redistributions of source code must retain the above copyright
! 9: * notice, this list of conditions and the following disclaimer.
! 10: * 2. Redistributions in binary form must reproduce the above copyright
! 11: * notice, this list of conditions and the following disclaimer in the
! 12: * documentation and/or other materials provided with the distribution.
! 13: *
! 14: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 15: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 16: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
! 17: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
! 18: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 19: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 20: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 21: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
! 22: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
! 23: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 24: * POSSIBILITY OF SUCH DAMAGE.
! 25: */
! 26:
! 27: #ifndef _SOLBOURNE_KAP_H_
! 28: #define _SOLBOURNE_KAP_H_
! 29:
! 30: /*
! 31: * KAP specific control registers
! 32: */
! 33:
! 34: #ifdef _KERNEL
! 35:
! 36: /* TLB handling - write only */
! 37: #define ASI_GTLB_RANDOM 0xc0 /* random TLB drop-in */
! 38: #define ASI_GTLB_DROPIN 0xc1 /* TLB drop-in */
! 39: #define ASI_GTLB_INVAL_ENTRY 0xc2 /* invalidate entry */
! 40: #define ASI_GTLB_INVAL_PID 0xc3 /* invalidate PID */
! 41: #define ASI_GTLB_INVALIDATE 0xc4 /* invalidate entire TLB */
! 42: #define ASI_ITLB_DROPIN 0xc8 /* iTLB drop-in */
! 43:
! 44: /* TLB position addressing */
! 45: #define TLB_SLOT(x) ((x) << 3)
! 46: #define TLB_INCR (1 << 3)
! 47: #define GTLB_SLOTS (128 + 8) /* XXX unsure */
! 48: #define ITLB_SLOTS 8 /* XXX unsure */
! 49:
! 50: /* data cache handling - read only except ASI_DCACHE_RW */
! 51: #define ASI_DCACHE_FLUSH 0xd0 /* flush dcache block */
! 52: #define ASI_DCACHE_LOOKUP 0xd1 /* check for dcache hit */
! 53: #define ASI_DCACHE_RW 0xd2 /* read/write dcache */
! 54: #define ASI_DCACHE_INVAL 0xd3 /* invalidate dcache */
! 55:
! 56: /* cache line addressing (for D flushes) */
! 57: #define DCACHE_LINE(x) ((x) << 2)
! 58: #define DCACHE_INCR (1 << 2)
! 59: #define DCACHE_LINES 256
! 60:
! 61: /* bus access - read/write */
! 62: #define ASI_PHYS_IO 0xd4 /* not cached */
! 63: #define ASI_PHYS_CACHED 0xd5 /* cached */
! 64: #define ASI_PHYS_NBW 0xd6 /* non byte writeable shared */
! 65: #define ASI_PHYS_BW 0xd7 /* byte writeable shared */
! 66:
! 67: /* inst cache handling - read only except ASI_ICACHE_RW */
! 68: #define ASI_ICACHE_LOOKUP 0xd9 /* check for icache hit */
! 69: #define ASI_ICACHE_RW 0xda /* read/write icache */
! 70: #define ASI_ICACHE_INVAL 0xdb /* invalidate icache */
! 71:
! 72: /* MMU registers */
! 73: #define ASI_MMCR 0xe0 /* control register, rw */
! 74: #define ASI_PDBR 0xe1 /* page directory base address, rw */
! 75: #define ASI_FVAR 0xe2 /* fault va, rw */
! 76: #define ASI_PDER 0xe3 /* page directory entry pointer, ro */
! 77: #define ASI_PTOR 0xe4 /* page table offset, ro */
! 78: #define ASI_FPAR 0xe5 /* fault pa, rw */
! 79: #define ASI_FPSR 0xe6 /* fault ASI, rw */
! 80: #define ASI_PIID 0xe7 /* process ID invalidation, rw */
! 81: #define ASI_PID 0xe8 /* process ID, rw */
! 82: #define ASI_BCR 0xe9 /* bus control, rw */
! 83: #define ASI_FCR 0xea /* fault cause, rw */
! 84: #define ASI_PTW0 0xeb /* translation window #0, rw */
! 85: #define ASI_PTW1 0xec /* translation window #0, rw */
! 86: #define ASI_PTW2 0xed /* translation window #0, rw */
! 87:
! 88: /* Hardware watchdog */
! 89: #define ASI_WAR0 0xee /* watchpoint address 0, rw */
! 90: #define ASI_WAR1 0xef /* watchpoint address 1, rw */
! 91: #define ASI_WCR 0xf0 /* watchpoint control register, rw */
! 92:
! 93: /* MMCR fields */
! 94: #define MMCR_ENABLE 0x00000001 /* MMU enable */
! 95: #define MMCR_MATCH_PTW 0x00000002 /* lookup matches PTW */
! 96: #define MMCR_MATCH_ITLB 0x00000004 /* lookup matches ITLB */
! 97: #define MMCR_MATCH_GTLB 0x00000008 /* lookup matches GTLB */
! 98: #define MMCR_ISET0 0x00000080 /* icache set 0 */
! 99: #define MMCR_ISET1 0x00000100 /* icache set 1 */
! 100: #define MMCR_ISET2 0x00000200 /* icache set 2 */
! 101: #define MMCR_DSET0 0x00000400 /* dcache set 0 */
! 102: #define MMCR_DSET1 0x00000800 /* dcache set 1 */
! 103:
! 104: /* BCR fields */
! 105: #define BCR_FAULT_SYNDROME 0x000000ff /* ECC syndrome byte */
! 106: #define BCR_ECC 0x00000100 /* ECC enable */
! 107: #define BCR_FAULT_DISABLE 0x00000200 /* disable ECC faults */
! 108:
! 109: /* FCR fields */
! 110: #define FCR_PROTMASK 0x0000000f
! 111: #define FCR_V 0x00000001 /* page not valid */
! 112: #define FCR_RO 0x00000002 /* write access on read only */
! 113: #define FCR_S 0x00000004 /* user access on sup. only */
! 114: #define FCR_EXTERNAL 0x00000100 /* external fault */
! 115: #define FCR_ECC_SINGLE 0x00000200 /* single bit ECC */
! 116: #define FCR_ECC_MULTIPLE 0x00000400 /* multiple bit ECC */
! 117:
! 118: #define FCR_BITS "\020\01V\02RO\03S\011EXTERNAL\012ECCS\013ECCM"
! 119:
! 120: /* PTW fields */
! 121: #define PTW_V 0x00000001 /* valid */
! 122: #define PTW_RO 0x00000002 /* read only */
! 123: #define PTW_RW 0x00000000
! 124: #define PTW_S 0x00000004 /* supervisor only */
! 125: #define PTW_CACHEABLE 0x00000008
! 126: #define PTW_BYTE_SHARED 0x00000010
! 127: #define PTW_SHARED 0x00000018
! 128: #define PTW_MASK_MASK 0x0000ff00 /* window address mask */
! 129: #define PTW_MASK_SHIFT 8
! 130: #define PTW_PA_MASK 0x00ff0000 /* physical window */
! 131: #define PTW_PA_SHIFT 16
! 132: #define PTW_VA_MASK 0xff000000 /* virtual window */
! 133: #define PTW_VA_SHIFT 24
! 134:
! 135: #define PTW_WINDOW_SIZE 0x01000000
! 136: #define PTW_WINDOW_MASK 0xff000000
! 137: #define PTW_WINDOW_SHIFT 24
! 138:
! 139: #define PTW_TEMPLATE(va,pa,size) \
! 140: (((va) << PTW_VA_SHIFT) | ((pa) << PTW_PA_SHIFT) | \
! 141: (((~((size) - 1) >> 24) << PTW_MASK_SHIFT) & PTW_MASK_MASK))
! 142:
! 143: /*
! 144: * Initial virtual memory settings
! 145: */
! 146:
! 147: #define ROM_WINDOW 0x00
! 148: #define PTW0_BASE (vaddr_t)(ROM_WINDOW << PTW_WINDOW_SHIFT)
! 149: #define PHYSMEM_WINDOW 0xf0
! 150: #define PHYSMEM_BASE (vaddr_t)(PHYSMEM_WINDOW << PTW_WINDOW_SHIFT)
! 151: #define PTW1_WINDOW 0xfd
! 152: #define PTW1_BASE (vaddr_t)(PTW1_WINDOW << PTW_WINDOW_SHIFT)
! 153: #define PTW2_WINDOW 0xfe
! 154: #define PTW2_BASE (vaddr_t)(PTW2_WINDOW << PTW_WINDOW_SHIFT)
! 155: #define PTW0_DEFAULT \
! 156: PTW_TEMPLATE(ROM_WINDOW, ROM_WINDOW, 0x10000000) | PTW_S | PTW_V
! 157: #define PTW1_DEFAULT PTW_CACHEABLE | \
! 158: PTW_TEMPLATE(PTW1_WINDOW, PHYSMEM_WINDOW, 0x01000000) | PTW_S | PTW_V
! 159: #define PTW2_DEFAULT PTW_SHARED | \
! 160: PTW_TEMPLATE(PTW2_WINDOW, PHYSMEM_WINDOW, 0x01000000) | PTW_S | PTW_V
! 161:
! 162: #define PTW0_TO_PHYS(va) (paddr_t)(va)
! 163: #define PTW1_TO_PHYS(va) (paddr_t)((va) - PTW1_BASE + PHYSMEM_BASE)
! 164: #define PTW2_TO_PHYS(va) (paddr_t)((va) - PTW2_BASE + PHYSMEM_BASE)
! 165:
! 166: #define PHYS_TO_PTW0(pa) (vaddr_t)(pa)
! 167: #define PHYS_TO_PTW1(pa) (vaddr_t)((pa) - PHYSMEM_BASE + PTW1_BASE)
! 168: #define PHYS_TO_PTW2(pa) (vaddr_t)((pa) - PHYSMEM_BASE + PTW2_BASE)
! 169:
! 170: #endif /* _KERNEL */
! 171:
! 172: #endif /* _SOLBOURNE_KAP_H_ */
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