Annotation of sys/arch/solbourne/include/idt.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: idt.h,v 1.1 2005/04/19 21:30:17 miod Exp $ */
! 2: /*
! 3: * Copyright (c) 2005, Miodrag Vallat
! 4: *
! 5: * Redistribution and use in source and binary forms, with or without
! 6: * modification, are permitted provided that the following conditions
! 7: * are met:
! 8: * 1. Redistributions of source code must retain the above copyright
! 9: * notice, this list of conditions and the following disclaimer.
! 10: * 2. Redistributions in binary form must reproduce the above copyright
! 11: * notice, this list of conditions and the following disclaimer in the
! 12: * documentation and/or other materials provided with the distribution.
! 13: *
! 14: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 15: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 16: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
! 17: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
! 18: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 19: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 20: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 21: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
! 22: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
! 23: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 24: * POSSIBILITY OF SUCH DAMAGE.
! 25: */
! 26:
! 27: #ifndef _SOLBOURNE_IDT_H_
! 28: #define _SOLBOURNE_IDT_H_
! 29:
! 30: /*
! 31: * Definitions for the core chips found on the IDT motherboard.
! 32: *
! 33: * All addresses are physical.
! 34: */
! 35:
! 36: /*
! 37: * iGLU: GLUE Logic
! 38: */
! 39:
! 40: #define GLU_BASE 0x60000000
! 41:
! 42: /* profiling timer (level 14) */
! 43: #define GLU_L14_DIVISOR 0x60000000
! 44: #define GLU_L14_RESOLUTION (256 / 5) /* in microseconds */
! 45: #define GLU_L14_ENABLE 0x60000008
! 46: #define GLU_L14_IACK 0x6000000c
! 47:
! 48: /* scheduling timer (level 10) */
! 49: #define GLU_L10_IACK 0x60000800
! 50:
! 51: /* board status register */
! 52: #define GLU_BSR 0x60001800
! 53: #define GBSR_LED_MASK 0x07
! 54: #define GBSR_LED_OFF 00
! 55: #define GBSR_LED_AMBER 02
! 56: #define GBSR_LED_AMBER_BLINK 03
! 57: #define GBSR_LED_GREEN 04
! 58: #define GBSR_LED_GREEN_BLINK 05
! 59: #define GBSR_LED_BOTH_BLINK 07
! 60: #define GBSR_DIAG 0x08
! 61: #define GBSR_WARM 0x10
! 62: #define GBSR_NMI 0x20
! 63:
! 64: /* board diagnostic register */
! 65: #define GLU_DIAG 0x60001808
! 66: #define GD_EXTRA_MEMORY 0x10
! 67: #define GD_36MHZ 0x20
! 68: #define GD_L2_CACHE 0x40
! 69:
! 70: /* interrupt control register */
! 71: #define GLU_ICR 0x60002000
! 72: #define GICR_DISPATCH_MASK 0x0000000f /* post a software interrupt */
! 73: #define GICR_DISABLE_ALL 0x00000010
! 74:
! 75: /* programmable interrupt levels for sbus and onboard audio */
! 76: #define GLU_SBUS1 0x60002008
! 77: #define GLU_SBUS2 0x60002010
! 78: #define GLU_SBUS3 0x60002018
! 79: #define GLU_SBUS4 0x60002020
! 80: #define GLU_SBUS5 0x60002028
! 81: #define GLU_SBUS6 0x60002030
! 82: #define GLU_SBUS7 0x60002038
! 83: #define GLU_AUDIO 0x60002040
! 84:
! 85: /* reset register */
! 86: #define GLU_RESET 0x60002800
! 87:
! 88: /* programmable base for on-board i/o devices */
! 89: #define GLU_IOBASE 0x60003800
! 90:
! 91: /*
! 92: * iMC: Memory Controller
! 93: */
! 94:
! 95: #define MC_BASE 0x70000000
! 96:
! 97: #define MC0_MCR 0x70000001
! 98: #define MC1_MCR 0x71000001 /* may be missing */
! 99: #define MCR_BANK1_AVAIL 0x08
! 100: #define MCR_BANK0_AVAIL 0x04
! 101: #define MCR_BANK1_32M 0x02
! 102: #define MCR_BANK0_32M 0x01
! 103:
! 104: /*
! 105: * iCU: DMA and Interrupt Controller
! 106: */
! 107:
! 108: #define ICU_BASE 0x50000000
! 109:
! 110: /* interrupt status register */
! 111: #define ICU_ISR 0x50000000
! 112: #define ISR_S0_DMA_SECC 0x00000001
! 113: #define ISR_S0_DMA_MECC 0x00000002
! 114: #define ISR_S0_DMA_SERR 0x00000004
! 115: #define ISR_S1_DMA_SECC 0x00000008
! 116: #define ISR_S1_DMA_MECC 0x00000010
! 117: #define ISR_S1_DMA_SERR 0x00000020
! 118: #define ISR_S2_DMA_SECC 0x00000040
! 119: #define ISR_S2_DMA_MECC 0x00000080
! 120: #define ISR_S2_DMA_SERR 0x00000100
! 121: #define ISR_EN_DMA_SECC 0x00000200
! 122: #define ISR_EN_DMA_MECC 0x00000400
! 123: #define ISR_EN_DMA_SERR 0x00000800
! 124: #define ISR_SCSI_DMA_SECC 0x00001000
! 125: #define ISR_SCSI_DMA_MECC 0x00002000
! 126: #define ISR_SCSI_DMA_SERR 0x00004000
! 127: #define ISR_RIO_NMI_ENABLE 0x00008000
! 128: #define ISR_DMA_NMI_ENABLE 0x00010000
! 129: #define ISR_ICU_INT_ENABLE 0x00020000
! 130: #define ISR_SECC_COUNT 0x003c0000
! 131: #define ISR_SECC_OVERFLOW 0x00400000
! 132: #define ISR_MEMDEC_MISS 0x00800000
! 133: #define ISR_XLAT_INVALID 0x01000000
! 134: #define ISR_WIN_MISS 0x02000000
! 135: #define ISR_FAULT 0x04000000
! 136: #define ISR_S0_RIO_ERR 0x08000000
! 137: #define ISR_S1_RIO_ERR 0x10000000
! 138: #define ISR_S2_RIO_ERR 0x20000000
! 139: #define ISR_EN_RIO_ERR 0x40000000
! 140: #define ISR_RIO_RETRY_TMO 0x80000000
! 141:
! 142: #define ISR_BITS "\020" \
! 143: "\01S0_SECC\02S0_MECC\03S0_SERR\04S1_SECC\05S1_MECC\06S1_SERR" \
! 144: "\07S2_SECC\10S2_MECC\11S2_SERR\12EN_SECC\13EN_MECC\14EN_SERR" \
! 145: "\15SCSI_SECC\16SCSSI_MECC\17SCSI_SERR\20RIO_NMIE\21DMA_NMIE\22ICU_IE" \
! 146: "\27SECC_OVERFLOW\30MEMDEC_MISS\31XLAT_INVALID\32WIN_MISS\33FAULT" \
! 147: "\34S0_RIO\35S1_RIO\36S2_RIO\37RIO_TMO"
! 148:
! 149: #define ICU_TIR 0x50000008
! 150:
! 151: #define ICU_TER 0x5000000c
! 152: #define TER_S0 0x00000002
! 153: #define TER_S1 0x00000004
! 154: #define TER_S2 0x00000008
! 155: #define TER_ETHERNET 0x00000010
! 156: #define TER_SCSI 0x00000020
! 157: #define TER_IO_DISABLE 0x00000040
! 158: #define TER_W_COMP_DIS 0x00000080
! 159:
! 160: #define ICU_TWR 0x50000010
! 161:
! 162: #define ICU_TRR 0x50000014
! 163:
! 164: #define ICU_CONF 0x50000018
! 165: #define CONF_ECC_ENABLE 0x00000004
! 166: #define CONF_NO_EXTRA_MEMORY 0x00000008
! 167: #define CONF_SBUS_25MHZ 0x00000020
! 168: #define CONF_SLOW_DMA_WRITE 0x00000080
! 169: #define CONF_SLOW_DMA_READ 0x00000100
! 170: #define CONF_ICACHE_DISABLE 0x00000400
! 171:
! 172: /*
! 173: * Onboard devices
! 174: */
! 175:
! 176: #define SE_BASE 0x40000000 /* scsi and ethernet */
! 177: #define NVRAM_BASE 0x80000000
! 178: #define ZS1_BASE 0x80004000
! 179: #define ZS0_BASE 0x80008000
! 180: #define FDC_BASE 0x8000c000
! 181: #define AUDIO_BASE 0x80010000
! 182: #define TODCLOCK_BASE 0x80014000
! 183:
! 184: /* we map the following range 1:1 in kernel space */
! 185: #define OBIO_PA_START 0x80000000
! 186: #define OBIO_PA_END 0x80018000
! 187:
! 188: #endif /* _SOLBOURNE_IDT_H_ */
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