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Annotation of sys/arch/solbourne/dev/zsclock.c, Revision 1.1.1.1

1.1       nbrk        1: /*     $OpenBSD: zsclock.c,v 1.2 2005/04/20 01:43:51 miod Exp $        */
                      2: /*     $NetBSD: clock.c,v 1.11 1995/05/16 07:30:46 phil Exp $  */
                      3:
                      4: /*-
                      5:  * Copyright (c) 1990 The Regents of the University of California.
                      6:  * All rights reserved.
                      7:  *
                      8:  * This code is derived from software contributed to Berkeley by
                      9:  * William Jolitz and Don Ahn.
                     10:  *
                     11:  * Redistribution and use in source and binary forms, with or without
                     12:  * modification, are permitted provided that the following conditions
                     13:  * are met:
                     14:  * 1. Redistributions of source code must retain the above copyright
                     15:  *    notice, this list of conditions and the following disclaimer.
                     16:  * 2. Redistributions in binary form must reproduce the above copyright
                     17:  *    notice, this list of conditions and the following disclaimer in the
                     18:  *    documentation and/or other materials provided with the distribution.
                     19:  * 3. All advertising materials mentioning features or use of this software
                     20:  *    must display the following acknowledgement:
                     21:  *     This product includes software developed by the University of
                     22:  *     California, Berkeley and its contributors.
                     23:  * 4. Neither the name of the University nor the names of its contributors
                     24:  *    may be used to endorse or promote products derived from this software
                     25:  *    without specific prior written permission.
                     26:  *
                     27:  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
                     28:  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
                     29:  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
                     30:  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
                     31:  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
                     32:  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
                     33:  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
                     34:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
                     35:  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
                     36:  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
                     37:  * SUCH DAMAGE.
                     38:  *
                     39:  *     @(#)clock.c     7.2 (Berkeley) 5/12/91
                     40:  *
                     41:  */
                     42:
                     43: /*
                     44:  * Primitive clock interrupt routines.
                     45:  *
                     46:  * Improved by Phil Budne ... 10/17/94.
                     47:  * Pulled over code from i386/isa/clock.c (Matthias Pfaller 12/03/94).
                     48:  */
                     49:
                     50: #include <sys/param.h>
                     51: #include <sys/time.h>
                     52: #include <sys/kernel.h>
                     53: #include <sys/systm.h>
                     54: #include <sys/proc.h>
                     55: #include <sys/device.h>
                     56: #include <sys/conf.h>
                     57: #include <sys/ioctl.h>
                     58: #include <sys/kernel.h>
                     59:
                     60: #include <sparc/dev/z8530reg.h>
                     61: #include <machine/z8530var.h>
                     62:
                     63: #include <machine/autoconf.h>
                     64: #include <machine/cpu.h>
                     65:
                     66: /*
                     67:  * Zilog Z8530 Dual UART driver (clock interface)
                     68:  */
                     69:
                     70: /* Clock state.  */
                     71: struct zsclock_softc {
                     72:        struct device zsc_dev;
                     73:        struct zs_chanstate *zsc_cs;
                     74: };
                     75:
                     76: int    zsclock_match(struct device *, void *, void *);
                     77: void   zsclock_attach(struct device *, struct device *, void *);
                     78:
                     79: struct cfattach zsclock_ca = {
                     80:        sizeof(struct zsclock_softc), zsclock_match, zsclock_attach
                     81: };
                     82:
                     83: struct cfdriver zsclock_cd = {
                     84:        NULL, "zsclock", DV_DULL
                     85: };
                     86:
                     87: void   zsclock_stint(struct zs_chanstate *, int);
                     88:
                     89: struct zsops zsops_clock = {
                     90:        NULL,
                     91:        zsclock_stint,
                     92:        NULL,
                     93:        NULL
                     94: };
                     95:
                     96: static int zsclock_attached;
                     97:
                     98: /*
                     99:  * clock_match: how is this zs channel configured?
                    100:  */
                    101: int
                    102: zsclock_match(struct device *parent, void *match, void *aux)
                    103: {
                    104:        struct cfdata *cf = match;
                    105:        struct zsc_attach_args *args = aux;
                    106:
                    107:        /* only attach one instance */
                    108:        if (zsclock_attached)
                    109:                return (0);
                    110:
                    111:        /* make sure we'll win a probe over zstty or zskbd */
                    112:        if (cf->cf_loc[ZSCCF_CHANNEL] == args->channel)
                    113:                return (2 + 2);
                    114:
                    115:        if (cf->cf_loc[ZSCCF_CHANNEL] == ZSCCF_CHANNEL_DEFAULT)
                    116:                return (2 + 1);
                    117:
                    118:        return (0);
                    119: }
                    120:
                    121: /*
                    122:  * The Solbourne IDT systems provide a 4.9152 MHz clock to the ZS chips.
                    123:  */
                    124: #define        PCLK    (9600 * 512)    /* PCLK pin input clock rate */
                    125:
                    126: void
                    127: zsclock_attach(struct device *parent, struct device *self, void *aux)
                    128: {
                    129:        struct zsc_softc *zsc = (void *)parent;
                    130:        struct zsclock_softc *sc = (void *)self;
                    131:        struct zsc_attach_args *args = aux;
                    132:        struct zs_chanstate *cs;
                    133:        int channel;
                    134:        int reset, s, tconst;
                    135:
                    136:        channel = args->channel;
                    137:
                    138:        cs = &zsc->zsc_cs[channel];
                    139:        cs->cs_private = zsc;
                    140:        cs->cs_ops = &zsops_clock;
                    141:
                    142:        sc->zsc_cs = cs;
                    143:
                    144:        printf("\n");
                    145:
                    146:        hz = 100;
                    147:        tconst = ((PCLK / 2) / hz) - 2;
                    148:
                    149:        s = splclock();
                    150:
                    151:        reset = (channel == 0) ?  ZSWR9_A_RESET : ZSWR9_B_RESET;
                    152:        zs_write_reg(cs, 9, reset);
                    153:
                    154:        cs->cs_preg[1] = 0;
                    155:        cs->cs_preg[3] = ZSWR3_RX_8 | ZSWR3_RX_ENABLE;
                    156:        cs->cs_preg[4] = ZSWR4_CLK_X1 | ZSWR4_ONESB | ZSWR4_PARENB;
                    157:        cs->cs_preg[5] = ZSWR5_TX_8 | ZSWR5_TX_ENABLE;
                    158:        cs->cs_preg[9] = ZSWR9_MASTER_IE;
                    159:        cs->cs_preg[10] = 0;
                    160:        cs->cs_preg[11] = ZSWR11_RXCLK_RTXC | ZSWR11_TXCLK_RTXC |
                    161:            ZSWR11_TRXC_OUT_ENA | ZSWR11_TRXC_BAUD;
                    162:        cs->cs_preg[12] = tconst;
                    163:        cs->cs_preg[13] = tconst >> 8;
                    164:        cs->cs_preg[14] = ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA;
                    165:        cs->cs_preg[15] = ZSWR15_ZERO_COUNT_IE;
                    166:
                    167:        zs_loadchannelregs(cs);
                    168:
                    169:        splx(s);
                    170:
                    171:        /* enable interrupts */
                    172:        cs->cs_preg[1] |= ZSWR1_SIE;
                    173:        zs_write_reg(cs, 1, cs->cs_preg[1]);
                    174:
                    175:        zsclock_attached = 1;
                    176: }
                    177:
                    178: void
                    179: zsclock_stint(struct zs_chanstate *cs, int force)
                    180: {
                    181:        u_char rr0;
                    182:
                    183:        rr0 = zs_read_csr(cs);
                    184:        cs->cs_rr0 = rr0;
                    185:
                    186:        /*
                    187:         * Retrigger the interrupt as a soft interrupt, because we need
                    188:         * a trap frame for hardclock().
                    189:         */
                    190:        ienab_bis(IE_L10);
                    191:
                    192:        zs_write_csr(cs, ZSWR0_RESET_STATUS);
                    193: }

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