Annotation of sys/arch/solbourne/dev/todreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: todreg.h,v 1.1 2005/04/20 01:00:16 miod Exp $ */
2: /*
3: * Copyright (c) 2005, Miodrag Vallat
4: *
5: * Redistribution and use in source and binary forms, with or without
6: * modification, are permitted provided that the following conditions
7: * are met:
8: * 1. Redistributions of source code must retain the above copyright
9: * notice, this list of conditions and the following disclaimer.
10: * 2. Redistributions in binary form must reproduce the above copyright
11: * notice, this list of conditions and the following disclaimer in the
12: * documentation and/or other materials provided with the distribution.
13: *
14: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24: * POSSIBILITY OF SUCH DAMAGE.
25: */
26:
27: /*
28: * Oki MSM62X42BRS registers.
29: *
30: * A datasheet for this chip is available from:
31: * http://www.datasheetarchive.com/datasheet/pdf/19/196099.html
32: */
33:
34: #define MSM_REG(x) ((x) << 3)
35:
36: #define MSM_SEC_UNITS MSM_REG(0) /* seconds, low digit */
37: #define MSM_SEC_TENS MSM_REG(1) /* seconds, high digit */
38: #define MSM_MIN_UNITS MSM_REG(2) /* minutes, low digit */
39: #define MSM_MIN_TENS MSM_REG(3) /* minutes, high digit */
40: #define MSM_HOUR_UNITS MSM_REG(4) /* hours, low digit */
41: #define MSM_HOUR_TENS MSM_REG(5) /* hours, high digit */
42: #define MSM_HOUR_PM 0x04 /* PM bit if PM mode */
43: #define MSM_DAY_UNITS MSM_REG(6) /* day, low digit */
44: #define MSM_DAY_TENS MSM_REG(7) /* day, high digit */
45: #define MSM_MONTH_UNITS MSM_REG(8) /* month, low digit */
46: #define MSM_MONTH_TENS MSM_REG(9) /* month, high digit */
47: #define MSM_YEAR_UNITS MSM_REG(10) /* year, low digit */
48: #define MSM_YEAR_TENS MSM_REG(11) /* year, high digit */
49: #define CLOCK_YEAR_BASE 1968
50: #define MSM_DOW MSM_REG(12) /* day of week, 0 = sunday */
51:
52: #define MSM_D MSM_REG(13) /* control register D */
53: #define MSM_D_HOLD 0x01 /* hold clock for access */
54: #define MSM_D_BUSY 0x02 /* clock is busy */
55: #define MSM_D_INTR 0x04 /* interrupt pending */
56: #define MSM_D_30 0x08 /* 30 seconds adjustment */
57:
58: #define MSM_E MSM_REG(14) /* control register E */
59: #define MSM_E_MASK 0x01 /* output mask (set to disable) */
60: #define MSM_E_INTR 0x02 /* output interrupts (1) or pulse (0) */
61: #define MSM_E_PERIOD 0x04 /* interrupt (or pulse) period - needs
62: to be written twice! (2 bits) */
63: #define MSM_PERIOD_64HZ 0x00
64: #define MSM_PERIOD_1HZ 0x01
65: #define MSM_PERIOD_1MIN 0x10
66: #define MSM_PERIOD_1HOUR 0x11
67:
68: #define MSM_F MSM_REG(15) /* control register F */
69: #define MSM_F_RESET 0x01 /* reset clock */
70: #define MSM_F_STOP 0x02 /* stop clock */
71: #define MSM_F_24HR 0x04 /* 24 hour mode (valid on reset only) */
72: #define MSM_F_TEST 0x08 /* assert test signal */
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