Annotation of sys/arch/sh/sh/cache.c, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: cache.c,v 1.3 2007/03/05 21:48:23 miod Exp $ */
! 2: /* $NetBSD: cache.c,v 1.11 2006/01/02 23:37:34 uwe Exp $ */
! 3:
! 4: /*-
! 5: * Copyright (c) 2002 The NetBSD Foundation, Inc.
! 6: * All rights reserved.
! 7: *
! 8: * This code is derived from software contributed to The NetBSD Foundation
! 9: * by UCHIYAMA Yasushi.
! 10: *
! 11: * Redistribution and use in source and binary forms, with or without
! 12: * modification, are permitted provided that the following conditions
! 13: * are met:
! 14: * 1. Redistributions of source code must retain the above copyright
! 15: * notice, this list of conditions and the following disclaimer.
! 16: * 2. Redistributions in binary form must reproduce the above copyright
! 17: * notice, this list of conditions and the following disclaimer in the
! 18: * documentation and/or other materials provided with the distribution.
! 19: * 3. All advertising materials mentioning features or use of this software
! 20: * must display the following acknowledgement:
! 21: * This product includes software developed by the NetBSD
! 22: * Foundation, Inc. and its contributors.
! 23: * 4. Neither the name of The NetBSD Foundation nor the names of its
! 24: * contributors may be used to endorse or promote products derived
! 25: * from this software without specific prior written permission.
! 26: *
! 27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
! 28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
! 31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 37: * POSSIBILITY OF SUCH DAMAGE.
! 38: */
! 39:
! 40: #include <sys/param.h>
! 41: #include <sys/systm.h>
! 42:
! 43: #include <sh/cache.h>
! 44: #include <sh/cache_sh3.h>
! 45: #include <sh/cache_sh4.h>
! 46:
! 47: /*
! 48: * __cache_flush is used before sh_cache_config() is called.
! 49: */
! 50: static void __cache_flush(void);
! 51:
! 52: struct sh_cache_ops sh_cache_ops = {
! 53: ._icache_sync_all = (void (*)(void))__cache_flush,
! 54: ._icache_sync_range = (void (*)(vaddr_t, vsize_t))__cache_flush,
! 55: ._icache_sync_range_index = (void (*)(vaddr_t, vsize_t))__cache_flush,
! 56: ._dcache_wbinv_all = (void (*)(void))__cache_flush,
! 57: ._dcache_wbinv_range = (void (*)(vaddr_t, vsize_t))__cache_flush,
! 58: ._dcache_wbinv_range_index = (void (*)(vaddr_t, vsize_t))__cache_flush,
! 59: ._dcache_inv_range = (void (*)(vaddr_t, vsize_t))__cache_flush,
! 60: ._dcache_wb_range = (void (*)(vaddr_t, vsize_t))__cache_flush
! 61: };
! 62:
! 63: int sh_cache_enable_icache;
! 64: int sh_cache_enable_dcache;
! 65: int sh_cache_write_through;
! 66: int sh_cache_write_through_p0_u0_p3;
! 67: int sh_cache_write_through_p1;
! 68: int sh_cache_unified;
! 69: int sh_cache_ways;
! 70: int sh_cache_size_icache;
! 71: int sh_cache_size_dcache;
! 72: int sh_cache_line_size;
! 73: int sh_cache_ram_mode;
! 74: int sh_cache_index_mode_icache;
! 75: int sh_cache_index_mode_dcache;
! 76: int sh_cache_prefer_mask;
! 77:
! 78: void
! 79: sh_cache_init()
! 80: {
! 81: #ifdef CACHE_DEBUG
! 82: return;
! 83: #endif
! 84: #ifdef SH3
! 85: if (CPU_IS_SH3)
! 86: sh3_cache_config();
! 87: #endif
! 88: #ifdef SH4
! 89: if (CPU_IS_SH4)
! 90: sh4_cache_config();
! 91: #endif
! 92: }
! 93:
! 94: void
! 95: sh_cache_information()
! 96: {
! 97: #ifdef CACHE_DEBUG
! 98: printf("*** USE CPU INDEPENDENT CACHE OPS. ***\n");
! 99: return;
! 100: #endif
! 101:
! 102: /* I-cache or I/D-unified cache */
! 103: printf("cpu0: %dKB/%dB",
! 104: sh_cache_size_icache >> 10, sh_cache_line_size);
! 105: if (sh_cache_ways > 1)
! 106: printf(" %d-way associative", sh_cache_ways);
! 107: else
! 108: printf(" direct");
! 109: if (sh_cache_unified)
! 110: printf(" I/D-");
! 111: else
! 112: printf(" I-");
! 113: printf("cache");
! 114: if (!sh_cache_enable_icache)
! 115: printf(" DISABLED");
! 116: if (sh_cache_unified && sh_cache_ram_mode)
! 117: printf(" RAM-mode");
! 118: if (sh_cache_index_mode_icache)
! 119: printf(" INDEX-mode");
! 120:
! 121: /* D-cache */
! 122: if (!sh_cache_unified) {
! 123: printf(", %dKB/%dB", sh_cache_size_dcache >> 10,
! 124: sh_cache_line_size);
! 125: if (sh_cache_ways > 1)
! 126: printf(" %d-way associative", sh_cache_ways);
! 127: else
! 128: printf(" direct");
! 129: printf(" D-cache");
! 130: if (!sh_cache_enable_dcache)
! 131: printf(" DISABLED");
! 132: if (sh_cache_ram_mode)
! 133: printf(" RAM-mode");
! 134: if (sh_cache_index_mode_dcache)
! 135: printf(" INDEX-mode");
! 136: }
! 137: printf("\n");
! 138:
! 139: #ifdef CACHE_DEBUG
! 140: /* Write-through/back */
! 141: printf("cpu0: P0, U0, P3 write-%s; P1 write-%s\n",
! 142: sh_cache_write_through_p0_u0_p3 ? "through" : "back",
! 143: sh_cache_write_through_p1 ? "through" : "back");
! 144: #endif
! 145: }
! 146:
! 147: /*
! 148: * CPU-independent cache flush.
! 149: */
! 150: void
! 151: __cache_flush()
! 152: {
! 153: volatile int *p = (int *)SH3_PHYS_TO_P1SEG(IOM_RAM_BEGIN);
! 154: int i;
! 155: int d;
! 156:
! 157: /* Flush D-Cache */
! 158: /*
! 159: * Access address range [13:4].
! 160: * max:
! 161: * 16KB line-size 16B 4-way ... [11:4] * 4
! 162: * 16KB line-size 32B 1-way ... [13:5]
! 163: */
! 164: for (i = 0; i < 256/*entry*/ * 4/*way*/; i++) {
! 165: d = *p;
! 166: p += 4; /* next line index (16B) */
! 167: }
! 168:
! 169: /* Flush I-Cache */
! 170: /*
! 171: * this code flush I-cache. but can't compile..
! 172: * __asm volatile(".space 8192");
! 173: *
! 174: */
! 175: }
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