Annotation of sys/arch/sh/include/mmu_sh4.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: mmu_sh4.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $ */
2: /* $NetBSD: mmu_sh4.h,v 1.6 2006/03/04 01:55:03 uwe Exp $ */
3:
4: /*-
5: * Copyright (c) 2002 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by UCHIYAMA Yasushi.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
38: */
39:
40: #ifndef _SH_MMU_SH4_H_
41: #define _SH_MMU_SH4_H_
42: #include <sh/devreg.h>
43:
44: /* ITLB 4-entry full-associative UTLB 64-entry full-associative */
45: #define SH4_PTEH 0xff000000
46: #define SH4_PTEH_VPN_MASK 0xfffffc00
47: #define SH4_PTEH_ASID_MASK 0x000000ff
48: #define SH4_PTEL 0xff000004
49: #define SH4_PTEL_WT 0x00000001
50: #define SH4_PTEL_SH 0x00000002
51: #define SH4_PTEL_D 0x00000004
52: #define SH4_PTEL_C 0x00000008
53: #define SH4_PTEL_PR_SHIFT 5
54: #define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */
55: #define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */
56: #define SH4_PTEL_SZ_1K 0x00000000
57: #define SH4_PTEL_SZ_4K 0x00000010
58: #define SH4_PTEL_SZ_64K 0x00000080
59: #define SH4_PTEL_SZ_1M 0x00000090
60: #define SH4_PTEL_V 0x00000100
61: #define SH4_PTEL_HWBITS 0x1ffff1ff /* [28:12]PFN [8:0]attr. */
62:
63: #define SH4_PTEA 0xff000034
64: #define SH4_PTEA_SA_MASK 0x00000007
65: #define SH4_PTEA_SA_TC 0x00000008
66: #define SH4_TTB 0xff000008
67: #define SH4_TEA 0xff00000c
68: #define SH4_MMUCR 0xff000010
69: #define SH4_MMUCR_AT 0x00000001
70: #define SH4_MMUCR_TI 0x00000004
71: #define SH4_MMUCR_SV 0x00000100
72: #define SH4_MMUCR_SQMD 0x00000200
73: #define SH4_MMUCR_URC_SHIFT 10
74: #define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */
75: #define SH4_MMUCR_URB_SHIFT 18
76: #define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */
77: #define SH4_MMUCR_LRUI_SHIFT 26
78: #define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */
79:
80: #define SH4_MMUCR_MASK (SH4_MMUCR_LRUT_MASK | SH4_MMUCR_URB_MASK | \
81: SH4_MMUCR_URC_MASK | SH4_MMUCR_SQMD | SH4_MMUCR_SV | SH4_MMUCR_AT)
82: /*
83: * memory-mapped TLB
84: * must be access from P2-area program.
85: * branch to the other area must be maed at least 8 instruction
86: * after access.
87: */
88: #define SH4_ITLB_ENTRY 4
89: #define SH4_UTLB_ENTRY 64
90:
91: /* ITLB */
92: #define SH4_ITLB_AA 0xf2000000
93: /* address specification (common for address and data array(0,1)) */
94: #define SH4_ITLB_E_SHIFT 8
95: #define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */
96: /* data specification */
97: /* address-array */
98: #define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */
99: #define SH4_ITLB_AA_V 0x00000100
100: #define SH4_ITLB_AA_VPN_SHIFT 10
101: #define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */
102: /* data-array 1 */
103: #define SH4_ITLB_DA1 0xf3000000
104: #define SH4_ITLB_DA1_SH 0x00000002
105: #define SH4_ITLB_DA1_C 0x00000008
106: #define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */
107: #define SH4_ITLB_DA1_SZ_1K 0x00000000
108: #define SH4_ITLB_DA1_SZ_4K 0x00000010
109: #define SH4_ITLB_DA1_SZ_64K 0x00000080
110: #define SH4_ITLB_DA1_SZ_1M 0x00000090
111: #define SH4_ITLB_DA1_PR 0x00000040
112: #define SH4_ITLB_DA1_V 0x00000100
113: #define SH4_ITLB_DA1_PPN_SHIFT 11
114: #define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */
115: /* data-array 2 */
116: #define SH4_ITLB_DA2 0xf3800000
117: #define SH4_ITLB_DA2_SA_MASK 0x00000003
118: #define SH4_ITLB_DA2_TC 0x00000004
119:
120: /* UTLB */
121: #define SH4_UTLB_AA 0xf6000000
122: /* address specification (common for address and data array(0,1)) */
123: #define SH4_UTLB_E_SHIFT 8
124: #define SH4_UTLB_E_MASK 0x00003f00
125: #define SH4_UTLB_A 0x00000080
126: /* data specification */
127: /* address-array */
128: #define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */
129: #define SH4_UTLB_AA_D 0x00000200
130: #define SH4_UTLB_AA_V 0x00000100
131: #define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */
132: /* data-array 1 */
133: #define SH4_UTLB_DA1 0xf7000000
134: #define SH4_UTLB_DA1_WT 0x00000001
135: #define SH4_UTLB_DA1_SH 0x00000002
136: #define SH4_UTLB_DA1_D 0x00000004
137: #define SH4_UTLB_DA1_C 0x00000008
138: #define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */
139: #define SH4_UTLB_DA1_SZ_1K 0x00000000
140: #define SH4_UTLB_DA1_SZ_4K 0x00000010
141: #define SH4_UTLB_DA1_SZ_64K 0x00000080
142: #define SH4_UTLB_DA1_SZ_1M 0x00000090
143: #define SH4_UTLB_DA1_PR_SHIFT 5
144: #define SH4_UTLB_DA1_PR_MASK 0x00000060
145: #define SH4_UTLB_DA1_V 0x00000100
146: #define SH4_UTLB_DA1_PPN_SHIFT 11
147: #define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */
148: /* data-array 2 */
149: #define SH4_UTLB_DA2 0xf7800000
150: #define SH4_UTLB_DA2_SA_MASK 0x00000003
151: #define SH4_UTLB_DA2_TC 0x00000004
152:
153: #define SH4_TLB_DISABLE *(volatile uint32_t *)SH4_MMUCR = SH4_MMUCR_TI
154: #endif /* !_SH_MMU_SH4_H_ */
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