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1.1 nbrk 1: /* $OpenBSD: locore.h,v 1.3 2007/05/26 15:28:19 miod Exp $ */
2: /* $NetBSD: locore.h,v 1.11 2006/01/23 22:32:50 uwe Exp $ */
3:
4: /*-
5: * Copyright (c) 2002 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by the NetBSD
19: * Foundation, Inc. and its contributors.
20: * 4. Neither the name of The NetBSD Foundation nor the names of its
21: * contributors may be used to endorse or promote products derived
22: * from this software without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34: * POSSIBILITY OF SUCH DAMAGE.
35: */
36:
37: #if defined(SH3) && defined(SH4)
38: #define MOV(x, r) mov.l .L_/**/x, r; mov.l @r, r
39: #define REG_SYMBOL(x) .L_/**/x: .long _C_LABEL(__sh_/**/x)
40: #define FUNC_SYMBOL(x) .L_/**/x: .long _C_LABEL(__sh_/**/x)
41: #elif defined(SH3)
42: #define MOV(x, r) mov.l .L_/**/x, r
43: #define REG_SYMBOL(x) .L_/**/x: .long SH3_/**/x
44: #define FUNC_SYMBOL(x) .L_/**/x: .long _C_LABEL(sh3_/**/x)
45: #elif defined(SH4)
46: #define MOV(x, r) mov.l .L_/**/x, r
47: #define REG_SYMBOL(x) .L_/**/x: .long SH4_/**/x
48: #define FUNC_SYMBOL(x) .L_/**/x: .long _C_LABEL(sh4_/**/x)
49: #endif /* SH3 && SH4 */
50:
51: /*
52: * BANK1 r7 contains kernel stack top address.
53: * BANK1 r6 contains current frame pointer. (per process)
54: */
55: /*
56: * __EXCEPTION_ENTRY:
57: * + setup stack pointer
58: * + save all register to frame. (struct trapframe)
59: * + setup kernel stack.
60: * + change bank from 1 to 0
61: * + set BANK0 (r4, r5, r6) = (ssr, spc, ssp)
62: */
63: #define __EXCEPTION_ENTRY ;\
64: /* Check kernel/user mode. */ ;\
65: mov #0x40, r3 ;\
66: swap.b r3, r3 ;\
67: stc ssr, r2 ;\
68: swap.w r3, r3 /* r3 = 0x40000000 */ ;\
69: mov r2, r0 /* r2 = r0 = SSR */ ;\
70: and r3, r0 ;\
71: tst r0, r0 /* if (SSR.MD == 0) T = 1 */ ;\
72: mov r14, r1 ;\
73: mov r6, r14 /* frame pointer */ ;\
74: bf/s 1f /* T==0 ...Exception from kernel mode */;\
75: mov r15, r0 ;\
76: /* Exception from user mode */ ;\
77: mov r7, r15 /* change to kernel stack */ ;\
78: 1: ;\
79: /* Save registers */ ;\
80: mov.l r1, @-r14 /* tf_r14 */ ;\
81: mov.l r0, @-r14 /* tf_r15 */ ;\
82: stc.l r0_bank,@-r14 /* tf_r0 */ ;\
83: stc.l r1_bank,@-r14 /* tf_r1 */ ;\
84: stc.l r2_bank,@-r14 /* tf_r2 */ ;\
85: stc.l r3_bank,@-r14 /* tf_r3 */ ;\
86: stc.l r4_bank,@-r14 /* tf_r4 */ ;\
87: stc.l r5_bank,@-r14 /* tf_r5 */ ;\
88: stc.l r6_bank,@-r14 /* tf_r6 */ ;\
89: stc.l r7_bank,@-r14 /* tf_r7 */ ;\
90: mov.l r8, @-r14 /* tf_r8 */ ;\
91: mov.l r9, @-r14 /* tf_r9 */ ;\
92: mov.l r10, @-r14 /* tf_r10 */ ;\
93: mov.l r11, @-r14 /* tf_r11 */ ;\
94: mov.l r12, @-r14 /* tf_r12 */ ;\
95: mov.l r13, @-r14 /* tf_r13 */ ;\
96: sts.l pr, @-r14 /* tf_pr */ ;\
97: sts.l mach, @-r14 /* tf_mach*/ ;\
98: sts.l macl, @-r14 /* tf_macl*/ ;\
99: mov.l r2, @-r14 /* tf_ssr */ ;\
100: stc.l spc, @-r14 /* tf_spc */ ;\
101: add #-TF_SPC, r14 /* skip tf_ubc, tf_expevt */ ;\
102: mov r14, r6 /* store frame pointer */ ;\
103: /* Change register bank to 0 */ ;\
104: shlr r3 /* r3 = 0x20000000 */ ;\
105: stc sr, r1 /* r1 = SR */ ;\
106: not r3, r3 ;\
107: and r1, r3 ;\
108: ldc r3, sr /* SR.RB = 0 */ ;\
109: /* Set up argument. r4 = ssr, r5 = spc */ ;\
110: stc r2_bank,r4 ;\
111: stc spc, r5
112:
113: /*
114: * __EXCEPTION_RETURN:
115: * + block exception
116: * + restore all register from stack.
117: * + rte.
118: */
119: #define __EXCEPTION_RETURN ;\
120: mov #0x10, r0 ;\
121: swap.b r0, r0 ;\
122: swap.w r0, r0 /* r0 = 0x10000000 */ ;\
123: stc sr, r1 ;\
124: or r0, r1 ;\
125: ldc r1, sr /* SR.BL = 1 */ ;\
126: stc r6_bank,r0 ;\
127: mov r0, r14 ;\
128: add #TF_SIZE, r0 ;\
129: ldc r0, r6_bank /* roll up frame pointer */ ;\
130: add #TF_SPC, r14 /* skip tf_expevt, tf_ubc */ ;\
131: mov.l @r14+, r0 /* tf_spc */ ;\
132: ldc r0, spc ;\
133: mov.l @r14+, r0 /* tf_ssr */ ;\
134: ldc r0, ssr ;\
135: lds.l @r14+, macl /* tf_macl*/ ;\
136: lds.l @r14+, mach /* tf_mach*/ ;\
137: lds.l @r14+, pr /* tf_pr */ ;\
138: mov.l @r14+, r13 /* tf_r13 */ ;\
139: mov.l @r14+, r12 /* tf_r12 */ ;\
140: mov.l @r14+, r11 /* tf_r11 */ ;\
141: mov.l @r14+, r10 /* tf_r10 */ ;\
142: mov.l @r14+, r9 /* tf_r9 */ ;\
143: mov.l @r14+, r8 /* tf_r8 */ ;\
144: mov.l @r14+, r7 /* tf_r7 */ ;\
145: mov.l @r14+, r6 /* tf_r6 */ ;\
146: mov.l @r14+, r5 /* tf_r5 */ ;\
147: mov.l @r14+, r4 /* tf_r4 */ ;\
148: mov.l @r14+, r3 /* tf_r3 */ ;\
149: mov.l @r14+, r2 /* tf_r2 */ ;\
150: mov.l @r14+, r1 /* tf_r1 */ ;\
151: mov.l @r14+, r0 /* tf_r0 */ ;\
152: mov.l @r14+ r15 /* tf_r15 */ ;\
153: mov.l @r14+, r14 /* tf_r14 */ ;\
154: rte ;\
155: nop
156:
157:
158: /*
159: * Macros to disable and enable exceptions (including interrupts).
160: * This modifies SR.BL
161: */
162: #define __0x10 #0x10
163: #define __0x78 #0x78
164:
165: #define __EXCEPTION_BLOCK(Rn, Rm) ;\
166: mov __0x10, Rn ;\
167: swap.b Rn, Rn ;\
168: swap.w Rn, Rn /* Rn = 0x10000000 */ ;\
169: stc sr, Rm ;\
170: or Rn, Rm ;\
171: ldc Rm, sr /* block exceptions */
172:
173: #define __EXCEPTION_UNBLOCK(Rn, Rm) ;\
174: mov __0x10, Rn ;\
175: swap.b Rn, Rn ;\
176: swap.w Rn, Rn /* Rn = 0x10000000 */ ;\
177: not Rn, Rn ;\
178: stc sr, Rm ;\
179: and Rn, Rm ;\
180: ldc Rm, sr /* unblock exceptions */
181:
182: /*
183: * Macros to disable and enable interrupts.
184: * This modifies SR.I[0-3]
185: */
186: #define __INTR_MASK(Rn, Rm) ;\
187: mov __0x78, Rn ;\
188: shll Rn /* Rn = 0x000000f0 */ ;\
189: stc sr, Rm ;\
190: or Rn, Rm ;\
191: ldc Rm, sr /* mask all interrupt */
192:
193: #define __INTR_UNMASK(Rn, Rm) ;\
194: mov __0x78, Rn ;\
195: shll Rn /* Rn = 0x000000f0 */ ;\
196: not Rn, Rn ;\
197: stc sr, Rm ;\
198: and Rn, Rm ;\
199: ldc Rm, sr /* unmask all interrupt */
200:
201: #ifndef _LOCORE
202: void sh3_switch_setup(struct proc *);
203: void sh4_switch_setup(struct proc *);
204: void sh3_switch_resume(struct proc *);
205: void sh4_switch_resume(struct proc *);
206: extern void (*__sh_switch_resume)(struct proc *);
207: #endif /* !_LOCORE */