Annotation of sys/arch/sh/include/intr.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: intr.h,v 1.4 2007/06/21 04:37:54 miod Exp $ */
2: /* $NetBSD: intr.h,v 1.22 2006/01/24 23:51:42 uwe Exp $ */
3:
4: /*-
5: * Copyright (c) 2002 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: * 3. All advertising materials mentioning features or use of this software
17: * must display the following acknowledgement:
18: * This product includes software developed by the NetBSD
19: * Foundation, Inc. and its contributors.
20: * 4. Neither the name of The NetBSD Foundation nor the names of its
21: * contributors may be used to endorse or promote products derived
22: * from this software without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34: * POSSIBILITY OF SUCH DAMAGE.
35: */
36:
37: #ifndef _SH_INTR_H_
38: #define _SH_INTR_H_
39:
40: #ifdef _KERNEL
41:
42: #include <sys/device.h>
43: #include <sys/evcount.h>
44: #include <sys/lock.h>
45: #include <sys/queue.h>
46: #include <sh/psl.h>
47:
48: /* Interrupt sharing types. */
49: #define IST_NONE 0 /* none */
50: #define IST_PULSE 1 /* pulsed */
51: #define IST_EDGE 2 /* edge-triggered */
52: #define IST_LEVEL 3 /* level-triggered */
53:
54: /* Interrupt priority levels */
55: #define _IPL_N 15
56: #define _IPL_NSOFT 4
57:
58: #define IPL_NONE 0 /* nothing */
59: #define IPL_SOFT 1
60: #define IPL_SOFTCLOCK 2 /* timeouts */
61: #define IPL_SOFTNET 3 /* protocol stacks */
62: #define IPL_SOFTSERIAL 4 /* serial */
63:
64: #define IPL_SOFTNAMES { \
65: "misc", \
66: "clock", \
67: "net", \
68: "serial", \
69: }
70:
71: struct intc_intrhand {
72: int (*ih_func)(void *);
73: void *ih_arg;
74: int ih_level; /* SR.I[0:3] value */
75: int ih_evtcode; /* INTEVT or INTEVT2(SH7709/SH7709A) */
76: int ih_idx; /* evtcode -> intrhand mapping */
77: int ih_irq;
78: struct evcount ih_count;
79: const char *ih_name;
80: };
81:
82: /* from 0x200 by 0x20 -> from 0 by 1 */
83: #define EVTCODE_TO_MAP_INDEX(x) (((x) >> 5) - 0x10)
84: #define EVTCODE_TO_IH_INDEX(x) \
85: __intc_evtcode_to_ih[EVTCODE_TO_MAP_INDEX(x)]
86: #define EVTCODE_IH(x) (&__intc_intrhand[EVTCODE_TO_IH_INDEX(x)])
87: extern int8_t __intc_evtcode_to_ih[];
88: extern struct intc_intrhand __intc_intrhand[];
89:
90: void intc_init(void);
91: void *intc_intr_establish(int, int, int, int (*)(void *), void *, const char *);
92: void intc_intr_disestablish(void *);
93: void intc_intr_enable(int);
94: void intc_intr_disable(int);
95: void intc_intr(int, int, int);
96:
97: void intpri_intr_priority(int evtcode, int level);
98:
99: /*
100: * software simulated interrupt
101: */
102: struct sh_soft_intrhand {
103: TAILQ_ENTRY(sh_soft_intrhand) sih_q;
104: struct sh_soft_intr *sih_intrhead;
105: void (*sih_fn)(void *);
106: void *sih_arg;
107: int sih_pending;
108: };
109:
110: struct sh_soft_intr {
111: TAILQ_HEAD(, sh_soft_intrhand) softintr_q;
112: struct simplelock softintr_slock;
113: unsigned long softintr_ipl;
114: };
115:
116: #define softintr_schedule(arg) \
117: do { \
118: struct sh_soft_intrhand *__sih = (arg); \
119: struct sh_soft_intr *__si = __sih->sih_intrhead; \
120: int __s; \
121: \
122: __s = _cpu_intr_suspend(); \
123: simple_lock(&__si->softintr_slock); \
124: if (__sih->sih_pending == 0) { \
125: TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \
126: __sih->sih_pending = 1; \
127: setsoft(__si->softintr_ipl); \
128: } \
129: simple_unlock(&__si->softintr_slock); \
130: _cpu_intr_resume(__s); \
131: } while (/*CONSTCOND*/0)
132:
133: void softintr_init(void);
134: void *softintr_establish(int, void (*)(void *), void *);
135: void softintr_disestablish(void *);
136: void softintr_dispatch(int);
137: void setsoft(int);
138:
139: /* XXX For legacy software interrupts. */
140: extern struct sh_soft_intrhand *softnet_intrhand;
141:
142: #define setsoftnet() softintr_schedule(softnet_intrhand)
143:
144: #endif /* _KERNEL */
145:
146: #endif /* !_SH_INTR_H_ */
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