Annotation of sys/arch/sh/include/intcreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: intcreg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $ */
2: /* $NetBSD: intcreg.h,v 1.10 2005/12/11 12:18:58 christos Exp $ */
3:
4: /*-
5: * Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. The name of the author may not be used to endorse or promote products
16: * derived from this software without specific prior written permission.
17: *
18: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27: * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28: */
29:
30: #ifndef _SH_INTCREG_H_
31: #define _SH_INTCREG_H_
32: #include <sh/devreg.h>
33:
34: /*
35: * INTC
36: */
37: /* SH3 SH7708*, SH7709* common */
38: #define SH3_ICR0 0xfffffee0 /* 16bit */
39: #define SH3_IPRA 0xfffffee2 /* 16bit */
40: #define SH3_IPRB 0xfffffee4 /* 16bit */
41:
42: /* SH7709, SH7709A only */
43: #define SH7709_ICR1 0xa4000010 /* 16bit */
44: #define SH7709_ICR2 0xa4000012 /* 16bit */
45: #define SH7709_PINTER 0xa4000014 /* 16bit */
46: #define SH7709_IPRC 0xa4000016 /* 16bit */
47: #define SH7709_IPRD 0xa4000018 /* 16bit */
48: #define SH7709_IPRE 0xa400001a /* 16bit */
49: #define SH7709_IRR0 0xa4000004 /* 8bit */
50: #define SH7709_IRR1 0xa4000006 /* 8bit */
51: #define SH7709_IRR2 0xa4000008 /* 8bit */
52:
53: #define IPRC_IRQ3_MASK 0xf000
54: #define IPRC_IRQ2_MASK 0x0f00
55: #define IPRC_IRQ1_MASK 0x00f0
56: #define IPRC_IRQ0_MASK 0x000f
57:
58: #define IPRD_PINT07_MASK 0xf000
59: #define IPRD_PINT8F_MASK 0x0f00
60: #define IPRD_IRQ5_MASK 0x00f0
61: #define IPRD_IRQ4_MASK 0x000f
62:
63: #define IPRE_DMAC_MASK 0xf000
64: #define IPRE_IRDA_MASK 0x0f00
65: #define IPRE_SCIF_MASK 0x00f0
66: #define IPRE_ADC_MASK 0x000f
67:
68: #define IRR0_PINT8F 0x80
69: #define IRR0_PINT07 0x40
70: #define IRR0_IRQ5 0x20
71: #define IRR0_IRQ4 0x10
72: #define IRR0_IRQ3 0x08
73: #define IRR0_IRQ2 0x04
74: #define IRR0_IRQ1 0x02
75: #define IRR0_IRQ0 0x01
76:
77:
78: /* SH4 */
79: #define SH4_ICR 0xffd00000 /* 16bit */
80: #define SH4_IPRA 0xffd00004 /* 16bit */
81: #define SH4_IPRB 0xffd00008 /* 16bit */
82: #define SH4_IPRC 0xffd0000c /* 16bit */
83: #define SH4_IPRD 0xffd00010 /* 16bit */
84: #define SH4_INTPRI00 0xfe080000 /* 32bit */
85: #define SH4_INTREQ00 0xfe080020 /* 32bit */
86: #define SH4_INTMSK00 0xfe080040 /* 32bit */
87: #define SH4_INTMSKCLR00 0xfe080060 /* 32bit */
88:
89: #define IPRC_GPIO_MASK 0xf000
90: #define IPRC_DMAC_MASK 0x0f00
91: #define IPRC_SCIF_MASK 0x00f0
92: #define IPRC_HUDI_MASK 0x000f
93:
94: #define IPRD_IRL0_MASK 0xf000
95: #define IPRD_IRL1_MASK 0x0f00
96: #define IPRD_IRL2_MASK 0x00f0
97: #define IPRD_IRL3_MASK 0x000f
98:
99: #define IPRA_TMU0_MASK 0xf000
100: #define IPRA_TMU1_MASK 0x0f00
101: #define IPRA_TMU2_MASK 0x00f0
102: #define IPRA_RTC_MASK 0x000f
103:
104: #define IPRB_WDT_MASK 0xf000
105: #define IPRB_REF_MASK 0x0f00
106: #define IPRB_SCI_MASK 0x00f0
107:
108: #define INTPRI00_PCI0_MASK 0x0000000f
109: #define INTPRI00_PCI1_MASK 0x000000f0
110: #define INTPRI00_TMU3_MASK 0x00000f00
111: #define INTPRI00_TMU4_MASK 0x0000f000
112:
113: /* INTREQ/INTMSK/INTMSKCLR */
114: #define INTREQ00_PCISERR 0x00000001
115: #define INTREQ00_PCIDMA3 0x00000002
116: #define INTREQ00_PCIDMA2 0x00000004
117: #define INTREQ00_PCIDMA1 0x00000008
118: #define INTREQ00_PCIDMA0 0x00000010
119: #define INTREQ00_PCIPWON 0x00000020
120: #define INTREQ00_PCIPWDWN 0x00000040
121: #define INTREQ00_PCIERR 0x00000080
122: #define INTREQ00_TUNI3 0x00000100
123: #define INTREQ00_TUNI4 0x00000200
124:
125: #define INTMSK00_MASK_ALL 0x000003ff
126:
127: #endif /* !_SH_INTCREG_H_ */
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