Annotation of sys/arch/sh/include/fpu.h, Revision 1.1
1.1 ! nbrk 1: #ifndef _SH_FPU_H_
! 2: /* $OpenBSD: fpu.h,v 1.1 2006/11/05 18:57:20 miod Exp $ */
! 3: /*
! 4: * Copyright (c) 2006, Miodrag Vallat
! 5: *
! 6: * Redistribution and use in source and binary forms, with or without
! 7: * modification, are permitted provided that the following conditions
! 8: * are met:
! 9: * 1. Redistributions of source code must retain the above copyright
! 10: * notice, this list of conditions and the following disclaimer.
! 11: * 2. Redistributions in binary form must reproduce the above copyright
! 12: * notice, this list of conditions and the following disclaimer in the
! 13: * documentation and/or other materials provided with the distribution.
! 14: *
! 15: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 16: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 17: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
! 18: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
! 19: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 20: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 21: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 22: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
! 23: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
! 24: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 25: * POSSIBILITY OF SUCH DAMAGE.
! 26: */
! 27:
! 28: #define _SH_FPU_H_
! 29:
! 30: /*
! 31: * SH4{,a} FPU definitions
! 32: */
! 33:
! 34: /* FPSCR bits */
! 35:
! 36: #define FPSCR_RB 0x00200000 /* register bank */
! 37: #define FPSCR_SZ 0x00100000 /* transfer size mode */
! 38: #define FPSCR_PR 0x00080000 /* precision mode */
! 39: #define FPSCR_DN 0x00040000 /* denormalization mode */
! 40: #define FPSCR_CAUSE_MASK 0x0003f000 /* exception cause mask */
! 41: #define FPSCR_CAUSE_SHIFT 12
! 42: #define FPSCR_ENABLE_MASK 0x00000f80 /* exception enable mask */
! 43: #define FPSCR_ENABLE_SHIFT 7
! 44: #define FPSCR_FLAG_MASK 0x0000007c /* exception sticky mask */
! 45: #define FPSCR_FLAG_SHIFT 2
! 46: #define FPSCR_ROUNDING_MASK 0x00000003 /* rounding mask */
! 47:
! 48: /* FPSCR exception bits */
! 49:
! 50: #define FPEXC_E 0x20 /* FPU Error */
! 51: #define FPEXC_V 0x10 /* invalid operation */
! 52: #define FPEXC_Z 0x08 /* divide by zero */
! 53: #define FPEXC_O 0x04 /* overflow */
! 54: #define FPEXC_U 0x02 /* underflow */
! 55: #define FPEXC_I 0x01 /* inexact */
! 56:
! 57: #endif /* _SH_FPU_H_ */
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