Annotation of sys/arch/sh/include/cpu.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cpu.h,v 1.10 2007/06/06 17:15:12 deraadt Exp $ */
2: /* $NetBSD: cpu.h,v 1.41 2006/01/21 04:24:12 uwe Exp $ */
3:
4: /*-
5: * Copyright (c) 2002 The NetBSD Foundation, Inc. All rights reserved.
6: * Copyright (c) 1990 The Regents of the University of California.
7: * All rights reserved.
8: *
9: * This code is derived from software contributed to Berkeley by
10: * William Jolitz.
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: * 3. Neither the name of the University nor the names of its contributors
21: * may be used to endorse or promote products derived from this software
22: * without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34: * SUCH DAMAGE.
35: *
36: * @(#)cpu.h 5.4 (Berkeley) 5/9/91
37: */
38:
39: /*
40: * SH3/SH4 support.
41: *
42: * T.Horiuchi Brains Corp. 5/22/98
43: */
44:
45: #ifndef _SH_CPU_H_
46: #define _SH_CPU_H_
47:
48: #include <sh/psl.h>
49: #include <sh/frame.h>
50:
51: #ifdef _KERNEL
52:
53: /*
54: * Per-CPU information.
55: */
56:
57: #include <sys/sched.h>
58: struct cpu_info {
59: struct proc *ci_curproc;
60:
61: struct schedstate_percpu ci_schedstate; /* scheduler state */
62: };
63:
64: extern struct cpu_info cpu_info_store;
65: #define curcpu() (&cpu_info_store)
66: #define cpu_number() 0
67: #define CPU_IS_PRIMARY(ci) 1
68: #define CPU_INFO_ITERATOR int
69: #define CPU_INFO_FOREACH(cii, ci) \
70: for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL)
71:
72:
73: /*
74: * Arguments to hardclock and gatherstats encapsulate the previous
75: * machine state in an opaque clockframe.
76: */
77: struct clockframe {
78: int spc; /* program counter at time of interrupt */
79: int ssr; /* status register at time of interrupt */
80: int ssp; /* stack pointer at time of interrupt */
81: };
82:
83: #define CLKF_USERMODE(cf) (!KERNELMODE((cf)->ssr))
84: #define CLKF_BASEPRI(cf) (((cf)->ssr & 0xf0) == 0)
85: #define CLKF_PC(cf) ((cf)->spc)
86: #define CLKF_INTR(cf) 0 /* XXX */
87:
88: /*
89: * This is used during profiling to integrate system time. It can safely
90: * assume that the process is resident.
91: */
92: #define PROC_PC(p) \
93: (((struct trapframe *)(p)->p_md.md_regs)->tf_spc)
94:
95: /*
96: * Preempt the current process if in interrupt from user mode,
97: * or after the current trap/syscall if in system mode.
98: */
99: #define need_resched(ci) \
100: do { \
101: want_resched = 1; \
102: if (curproc != NULL) \
103: aston(curproc); \
104: } while (/*CONSTCOND*/0)
105:
106: /*
107: * Give a profiling tick to the current process when the user profiling
108: * buffer pages are invalid. On the MIPS, request an ast to send us
109: * through trap, marking the proc as needing a profiling tick.
110: */
111: #define need_proftick(p) aston(p)
112:
113: /*
114: * Notify the current process (p) that it has a signal pending,
115: * process as soon as possible.
116: */
117: #define signotify(p) aston(p)
118:
119: #define aston(p) ((p)->p_md.md_astpending = 1)
120:
121: extern int want_resched; /* need_resched() was called */
122:
123: #define cpu_wait(p) ((void)(p))
124: /*
125: * We need a machine-independent name for this.
126: */
127: #define DELAY(x) delay(x)
128: #endif /* _KERNEL */
129:
130: /*
131: * Logical address space of SH3/SH4 CPU.
132: */
133: #define SH3_PHYS_MASK 0x1fffffff
134:
135: #define SH3_P0SEG_BASE 0x00000000 /* TLB mapped, also U0SEG */
136: #define SH3_P0SEG_END 0x7fffffff
137: #define SH3_P1SEG_BASE 0x80000000 /* pa == va */
138: #define SH3_P1SEG_END 0x9fffffff
139: #define SH3_P2SEG_BASE 0xa0000000 /* pa == va, non-cacheable */
140: #define SH3_P2SEG_END 0xbfffffff
141: #define SH3_P3SEG_BASE 0xc0000000 /* TLB mapped, kernel mode */
142: #define SH3_P3SEG_END 0xdfffffff
143: #define SH3_P4SEG_BASE 0xe0000000 /* peripheral space */
144: #define SH3_P4SEG_END 0xffffffff
145:
146: #define SH3_P1SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK)
147: #define SH3_P2SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK)
148: #define SH3_PHYS_TO_P1SEG(x) ((uint32_t)(x) | SH3_P1SEG_BASE)
149: #define SH3_PHYS_TO_P2SEG(x) ((uint32_t)(x) | SH3_P2SEG_BASE)
150: #define SH3_P1SEG_TO_P2SEG(x) ((uint32_t)(x) | 0x20000000)
151: #define SH3_P2SEG_TO_P1SEG(x) ((uint32_t)(x) & ~0x20000000)
152:
153: #ifdef _KERNEL
154: #ifndef __lint__
155:
156: /* switch from P1 to P2 */
157: #define RUN_P2 do { \
158: void *p; \
159: p = &&P2; \
160: goto *(void *)SH3_P1SEG_TO_P2SEG(p); \
161: P2: (void)0; \
162: } while (0)
163:
164: /* switch from P2 to P1 */
165: #define RUN_P1 do { \
166: void *p; \
167: p = &&P1; \
168: __asm volatile("nop;nop;nop;nop;nop;nop;nop;nop"); \
169: goto *(void *)SH3_P2SEG_TO_P1SEG(p); \
170: P1: (void)0; \
171: } while (0)
172:
173: #else /* __lint__ */
174: #define RUN_P2 do {} while (/* CONSTCOND */ 0)
175: #define RUN_P1 do {} while (/* CONSTCOND */ 0)
176: #endif
177: #endif
178:
179: #if defined(SH4)
180: /* SH4 Processor Version Register */
181: #define SH4_PVR_ADDR 0xff000030 /* P4 address */
182: #define SH4_PVR (*(volatile uint32_t *) SH4_PVR_ADDR)
183: #define SH4_PRR_ADDR 0xff000044 /* P4 address */
184: #define SH4_PRR (*(volatile uint32_t *) SH4_PRR_ADDR)
185:
186: #define SH4_PVR_MASK 0xffffff00
187: #define SH4_PVR_SH7750 0x04020500 /* SH7750 */
188: #define SH4_PVR_SH7750S 0x04020600 /* SH7750S */
189: #define SH4_PVR_SH775xR 0x04050000 /* SH775xR */
190: #define SH4_PVR_SH7751 0x04110000 /* SH7751 */
191:
192: #define SH4_PRR_MASK 0xfffffff0
193: #define SH4_PRR_7750R 0x00000100 /* SH7750R */
194: #define SH4_PRR_7751R 0x00000110 /* SH7751R */
195: #endif
196:
197: /*
198: * pull in #defines for kinds of processors
199: */
200: #include <machine/cputypes.h>
201:
202: #ifdef _KERNEL
203: void sh_cpu_init(int, int);
204: void sh_startup(void);
205: __dead void cpu_reset(void); /* soft reset */
206: void _cpu_spin(uint32_t); /* for delay loop. */
207: void delay(int);
208: struct pcb;
209: void savectx(struct pcb *);
210: struct fpreg;
211: void fpu_save(struct fpreg *);
212: void fpu_restore(struct fpreg *);
213: u_int cpu_dump(int (*)(dev_t, daddr64_t, caddr_t, size_t), daddr64_t *);
214: u_int cpu_dumpsize(void);
215: void dumpconf(void);
216: void dumpsys(void);
217: #endif /* _KERNEL */
218: #endif /* !_SH_CPU_H_ */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to cpu.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / sh / include