Annotation of sys/arch/sh/include/cache_sh4.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cache_sh4.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $ */
2: /* $NetBSD: cache_sh4.h,v 1.11 2006/03/04 01:55:03 uwe Exp $ */
3:
4: /*-
5: * Copyright (c) 2002 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by UCHIYAMA Yasushi.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
38: */
39:
40: /*
41: * SH4: SH7750 SH7750S SH7750R SH7751 SH7751R
42: */
43:
44: #ifndef _SH_CACHE_SH4_H_
45: #define _SH_CACHE_SH4_H_
46: #include <sh/devreg.h>
47: #ifdef _KERNEL
48:
49: #define SH4_ICACHE_SIZE 8192
50: #define SH4_DCACHE_SIZE 16384
51: #define SH4_EMODE_ICACHE_SIZE 16384
52: #define SH4_EMODE_DCACHE_SIZE 32768
53: #define SH4_CACHE_LINESZ 32
54:
55: #define SH4_CCR 0xff00001c
56: #define SH4_CCR_EMODE 0x80000000
57: #define SH4_CCR_IIX 0x00008000
58: #define SH4_CCR_ICI 0x00000800
59: #define SH4_CCR_ICE 0x00000100
60: #define SH4_CCR_OIX 0x00000080
61: #define SH4_CCR_ORA 0x00000020
62: #define SH4_CCR_OCI 0x00000008
63: #define SH4_CCR_CB 0x00000004
64: #define SH4_CCR_WT 0x00000002
65: #define SH4_CCR_OCE 0x00000001
66:
67: #define SH4_QACR0 0xff000038
68: #define SH4_QACR1 0xff00003c
69: #define SH4_QACR_AREA_SHIFT 2
70: #define SH4_QACR_AREA_MASK 0x0000001c
71:
72: /* I-cache address/data array */
73: #define SH4_CCIA 0xf0000000
74: /* address specification */
75: #define CCIA_A 0x00000008 /* associate bit */
76: #define CCIA_ENTRY_SHIFT 5 /* line size 32B */
77: #define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */
78: #define CCIA_EMODE_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */
79: /* data specification */
80: #define CCIA_V 0x00000001
81: #define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */
82:
83: #define SH4_CCID 0xf1000000
84: /* address specification */
85: #define CCID_L_SHIFT 2
86: #define CCID_L_MASK 0x1c /* line-size is 32B */
87: #define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */
88:
89: /* D-cache address/data array */
90: #define SH4_CCDA 0xf4000000
91: /* address specification */
92: #define CCDA_A 0x00000008 /* associate bit */
93: #define CCDA_ENTRY_SHIFT 5 /* line size 32B */
94: #define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */
95: /* data specification */
96: #define CCDA_V 0x00000001
97: #define CCDA_U 0x00000002
98: #define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */
99:
100: #define SH4_CCDD 0xf5000000
101:
102: /* Store Queue */
103: #define SH4_SQ 0xe0000000
104:
105: /*
106: * cache flush macro for locore level code.
107: */
108: #define SH4_CACHE_FLUSH() \
109: do { \
110: uint32_t __e, __a; \
111: \
112: /* D-cache */ \
113: for (__e = 0; __e < (SH4_DCACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\
114: __a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \
115: (*(volatile uint32_t *)__a) &= ~(CCDA_U | CCDA_V); \
116: } \
117: /* I-cache */ \
118: for (__e = 0; __e < (SH4_ICACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\
119: __a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \
120: (*(volatile uint32_t *)__a) &= ~(CCIA_V); \
121: } \
122: } while(/*CONSTCOND*/0)
123:
124: #define SH4_EMODE_CACHE_FLUSH() \
125: do { \
126: uint32_t __e, __a; \
127: \
128: /* D-cache */ \
129: for (__e = 0;__e < (SH4_EMODE_DCACHE_SIZE / SH4_CACHE_LINESZ);__e++) {\
130: __a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \
131: (*(volatile uint32_t *)__a) &= ~(CCDA_U | CCDA_V); \
132: } \
133: /* I-cache */ \
134: for (__e = 0;__e < (SH4_EMODE_ICACHE_SIZE / SH4_CACHE_LINESZ);__e++) {\
135: __a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \
136: (*(volatile uint32_t *)__a) &= ~(CCIA_V); \
137: } \
138: } while(/*CONSTCOND*/0)
139:
140: #define SH7750_CACHE_FLUSH() SH4_CACHE_FLUSH()
141: #define SH7750S_CACHE_FLUSH() SH4_CACHE_FLUSH()
142: #define SH7751_CACHE_FLUSH() SH4_CACHE_FLUSH()
143: #if defined(SH4_CACHE_DISABLE_EMODE)
144: #define SH7750R_CACHE_FLUSH() SH4_CACHE_FLUSH()
145: #define SH7751R_CACHE_FLUSH() SH4_CACHE_FLUSH()
146: #else
147: #define SH7750R_CACHE_FLUSH() SH4_EMODE_CACHE_FLUSH()
148: #define SH7751R_CACHE_FLUSH() SH4_EMODE_CACHE_FLUSH()
149: #endif
150:
151: #ifndef _LOCORE
152: extern void sh4_cache_config(void);
153: #endif
154: #endif /* _KERNEL */
155: #endif /* !_SH_CACHE_SH4_H_ */
CVSweb