Annotation of sys/arch/sh/include/cache_sh3.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cache_sh3.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $ */
2: /* $NetBSD: cache_sh3.h,v 1.8 2006/03/04 01:55:03 uwe Exp $ */
3:
4: /*-
5: * Copyright (c) 2002 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by UCHIYAMA Yasushi.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
38: */
39:
40: /*
41: * SH3: SH7708, SH7708S, SH7708R, SH7709, SH7709A
42: */
43: #ifndef _SH_CACHE_SH3_H_
44: #define _SH_CACHE_SH3_H_
45: #include <sh/devreg.h>
46: #ifdef _KERNEL
47:
48: #define SH3_CCR 0xffffffec
49: #define SH3_CCR_CE 0x00000001
50: #define SH3_CCR_WT 0x00000002
51: /* SH7708 don't have CB bit */
52: #define SH3_CCR_CB 0x00000004
53: #define SH3_CCR_CF 0x00000008
54: /* SH7709A don't have RA bit */
55: #define SH3_CCR_RA 0x00000020
56:
57: /* SH7709A specific cache-lock control register */
58: #define SH7709A_CCR2 0xa40000b0
59: #define SH7709A_CCR2_W2LOCK 0x00000001
60: #define SH7709A_CCR2_W2LOAD 0x00000002
61: #define SH7709A_CCR2_W3LOCK 0x00000100
62: #define SH7709A_CCR2_W3LOAD 0x00000200
63:
64: #define SH3_CCA 0xf0000000
65: /* Address specification */
66: #define CCA_A 0x00000008
67: #define CCA_ENTRY_SHIFT 4
68: /* 8KB cache (SH7708, SH7708S, SH7708R, SH7709) */
69: #define CCA_8K_ENTRY 128
70: #define CCA_8K_ENTRY_MASK 0x000007f0 /* [10:4] */
71: #define CCA_8K_WAY_SHIFT 11
72: #define CCA_8K_WAY_MASK 0x00001800 /* [12:11] */
73: /* 16KB cache (SH7709A) */
74: #define CCA_16K_ENTRY 256
75: #define CCA_16K_ENTRY_MASK 0x00000ff0 /* [11:4] */
76: #define CCA_16K_WAY_SHIFT 12
77: #define CCA_16K_WAY_MASK 0x00003000 /* [13:12] */
78:
79: /* Data specification */
80: #define CCA_V 0x00000001
81: #define CCA_U 0x00000002
82: #define CCA_LRU_SHIFT 4
83: #define CCA_LRU_MASK 0x000003f0 /* [9:4] */
84: #define CCA_TAGADDR_SHIFT 10
85: #define CCA_TAGADDR_MASK 0xfffffc00 /* [31:10] */
86:
87: #define SH3_CCD 0xf1000000
88: /* Address specification */
89: #define CCD_L_SHIFT 2
90: #define CCD_L_MASK 0x0000000c /* [3:2] */
91: #define CCD_E_SHIFT 4
92: #define CCD_8K_E_MASK 0x000007f0 /* [10:4] */
93: #define CCD_16K_E_MASK 0x00000ff0 /* [11:4] */
94: #define CCD_8K_W_SHIFT 11
95: #define CCD_8K_W_MASK 0x00001800 /* [12:11] */
96: #define CCD_16K_W_SHIFT 12
97: #define CCD_16K_W_MASK 0x00003000 /* [13:12] */
98: /* Data specification */
99:
100: /*
101: * Configuration
102: */
103: #define SH3_CACHE_LINESZ 16
104: #define SH3_CACHE_NORMAL_WAY 4
105: #define SH3_CACHE_RAMMODE_WAY 2
106:
107: #define SH3_CACHE_8K_ENTRY 128
108: #define SH3_CACHE_8K_WAY_NORMAL 4
109: #define SH3_CACHE_8K_WAY_RAMMODE 2
110:
111: #define SH3_CACHE_16K_ENTRY 256
112: #define SH3_CACHE_16K_WAY 4
113:
114: /*
115: * cache flush macro for locore level code.
116: */
117: #define SH3_CACHE_8K_FLUSH(maxway) \
118: do { \
119: uint32_t __e, __w, __wa, __a; \
120: \
121: for (__w = 0; __w < maxway; __w++) { \
122: __wa = SH3_CCA | __w << CCA_8K_WAY_SHIFT; \
123: for (__e = 0; __e < CCA_8K_ENTRY; __e++) { \
124: __a = __wa |(__e << CCA_ENTRY_SHIFT); \
125: (*(volatile uint32_t *)__a) &= \
126: ~(CCA_U | CCA_V); \
127: } \
128: } \
129: } while (/*CONSTCOND*/0)
130:
131: #define SH3_CACHE_16K_FLUSH() \
132: do { \
133: uint32_t __e, __w, __wa, __a; \
134: \
135: for (__w = 0; __w < SH3_CACHE_16K_WAY; __w++) { \
136: __wa = SH3_CCA | __w << CCA_16K_WAY_SHIFT; \
137: for (__e = 0; __e < CCA_16K_ENTRY; __e++) { \
138: __a = __wa |(__e << CCA_ENTRY_SHIFT); \
139: (*(volatile uint32_t *)__a) &= \
140: ~(CCA_U | CCA_V); \
141: } \
142: } \
143: } while (/*CONSTCOND*/0)
144:
145: #define SH7708_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4)
146: #define SH7708_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2)
147: #define SH7708S_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4)
148: #define SH7708S_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2)
149: #define SH7708R_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4)
150: #define SH7708R_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2)
151: #define SH7709_CACHE_FLUSH() SH3_CACHE_8K_FLUSH(4)
152: #define SH7709_CACHE_FLUSH_RAMMODE() SH3_CACHE_8K_FLUSH(2)
153: #define SH7709A_CACHE_FLUSH() SH3_CACHE_16K_FLUSH()
154:
155: #ifndef _LOCORE
156: extern void sh3_cache_config(void);
157: #endif
158: #endif /* _KERNEL */
159: #endif /* !_SH_CACHE_SH3_H_ */
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