Annotation of sys/arch/sh/include/cache.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cache.h,v 1.2 2007/03/05 21:48:21 miod Exp $ */
2: /* $NetBSD: cache.h,v 1.7 2006/01/21 00:46:36 uwe Exp $ */
3:
4: /*-
5: * Copyright (c) 2002 The NetBSD Foundation, Inc.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to The NetBSD Foundation
9: * by UCHIYAMA Yasushi.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. All advertising materials mentioning features or use of this software
20: * must display the following acknowledgement:
21: * This product includes software developed by the NetBSD
22: * Foundation, Inc. and its contributors.
23: * 4. Neither the name of The NetBSD Foundation nor the names of its
24: * contributors may be used to endorse or promote products derived
25: * from this software without specific prior written permission.
26: *
27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37: * POSSIBILITY OF SUCH DAMAGE.
38: */
39:
40: /*
41: * Cache configurations.
42: *
43: * SH3 I/D unified virtual-index physical-tag cache.
44: * SH4 I/D separated virtual-index physical-tag cache.
45: *
46: *
47: * size line-size entry way type
48: * SH7708 4/8K 16B 128 2/4 P0,P2,U0 [1]
49: * P1 [2]
50: * SH7709 4/8K 16B 128 2/4 [1]
51: * SH7709A 16K 16B 256 4 [1]
52: *
53: * SH7750 I$ D$ line-size entry way
54: * 8K 8/16K 32B 256 1 [1]
55: * SH7750
56: * SH7750S
57: * SH7751 I$ D$ line-size entry way
58: * 8K 8/16K 32B 256 1 [1]
59: *
60: * SH7750R
61: * SH7751R I$ D$ line-size entry way
62: * 16K 16/32K 32B 512 2 [1]
63: *
64: * [1] write-through/back selectable
65: * [2] write-through only
66: *
67: * Cache operations.
68: *
69: * There are some rules that must be followed:
70: *
71: * I-cache Sync (all or range):
72: * The goal is to synchronize the instruction stream,
73: * so you may need to write-back dirty data cache
74: * blocks first. If a range is requested, and you
75: * can't synchronize just a range, you have to hit
76: * the whole thing.
77: *
78: * D-cache Write-back Invalidate range:
79: * If you can't WB-Inv a range, you must WB-Inv the
80: * entire D-cache.
81: *
82: * D-cache Invalidate:
83: * If you can't Inv the D-cache without doing a
84: * Write-back, YOU MUST PANIC. This is to catch
85: * errors in calling code. Callers must be aware
86: * of this scenario, and must handle it appropriately
87: * (consider the bus_dma(9) operations).
88: *
89: * D-cache Write-back:
90: * If you can't Write-back without doing an invalidate,
91: * that's fine. Then treat this as a WB-Inv. Skipping
92: * the invalidate is merely an optimization.
93: *
94: * All operations:
95: * Valid virtual addresses must be passed to the
96: * cache operation.
97: *
98: *
99: * sh_icache_sync_all Synchronize I-cache
100: *
101: * sh_icache_sync_range Synchronize I-cache range
102: *
103: * sh_icache_sync_range_index (index ops)
104: *
105: * sh_dcache_wbinv_all Write-back Invalidate D-cache
106: *
107: * sh_dcache_wbinv_range Write-back Invalidate D-cache range
108: *
109: * sh_dcache_wbinv_range_index (index ops)
110: *
111: * sh_dcache_inv_range Invalidate D-cache range
112: *
113: * sh_dcache_wb_range Write-back D-cache range
114: *
115: * If I/D unified cache (SH3), I-cache ops are writeback invalidate
116: * operation.
117: * If write-through mode, sh_dcache_wb_range is no-operation.
118: *
119: */
120:
121: #ifndef _SH_CACHE_H_
122: #define _SH_CACHE_H_
123:
124: #ifdef _KERNEL
125: struct sh_cache_ops {
126: void (*_icache_sync_all)(void);
127: void (*_icache_sync_range)(vaddr_t, vsize_t);
128: void (*_icache_sync_range_index)(vaddr_t, vsize_t);
129:
130: void (*_dcache_wbinv_all)(void);
131: void (*_dcache_wbinv_range)(vaddr_t, vsize_t);
132: void (*_dcache_wbinv_range_index)(vaddr_t, vsize_t);
133: void (*_dcache_inv_range)(vaddr_t, vsize_t);
134: void (*_dcache_wb_range)(vaddr_t, vsize_t);
135: };
136:
137: /* Cache configurations */
138: #define sh_cache_enable_unified sh_cache_enable_icache
139: extern int sh_cache_enable_icache;
140: extern int sh_cache_enable_dcache;
141: extern int sh_cache_write_through;
142: extern int sh_cache_write_through_p0_u0_p3;
143: extern int sh_cache_write_through_p1;
144: extern int sh_cache_ways;
145: extern int sh_cache_unified;
146: #define sh_cache_size_unified sh_cache_size_icache
147: extern int sh_cache_size_icache;
148: extern int sh_cache_size_dcache;
149: extern int sh_cache_line_size;
150: /* for n-way set associative cache */
151: extern int sh_cache_way_size;
152: extern int sh_cache_way_shift;
153: extern int sh_cache_entry_mask;
154:
155: /* Special mode */
156: extern int sh_cache_ram_mode;
157: extern int sh_cache_index_mode_icache;
158: extern int sh_cache_index_mode_dcache;
159:
160: extern int sh_cache_prefer_mask;
161:
162: extern struct sh_cache_ops sh_cache_ops;
163:
164: #define sh_icache_sync_all() \
165: (*sh_cache_ops._icache_sync_all)()
166:
167: #define sh_icache_sync_range(v, s) \
168: (*sh_cache_ops._icache_sync_range)((v), (s))
169:
170: #define sh_icache_sync_range_index(v, s) \
171: (*sh_cache_ops._icache_sync_range_index)((v), (s))
172:
173: #define sh_dcache_wbinv_all() \
174: (*sh_cache_ops._dcache_wbinv_all)()
175:
176: #define sh_dcache_wbinv_range(v, s) \
177: (*sh_cache_ops._dcache_wbinv_range)((v), (s))
178:
179: #define sh_dcache_wbinv_range_index(v, s) \
180: (*sh_cache_ops._dcache_wbinv_range_index)((v), (s))
181:
182: #define sh_dcache_inv_range(v, s) \
183: (*sh_cache_ops._dcache_inv_range)((v), (s))
184:
185: #define sh_dcache_wb_range(v, s) \
186: (*sh_cache_ops._dcache_wb_range)((v), (s))
187:
188: void sh_cache_init(void);
189: void sh_cache_information(void);
190:
191: #define SH_HAS_UNIFIED_CACHE CPU_IS_SH3
192: #define SH_HAS_VIRTUAL_ALIAS CPU_IS_SH4
193: #define SH_HAS_WRITEBACK_CACHE (!sh_cache_write_through)
194:
195: #endif /* _KERNEL */
196: #endif /* _SH_CACHE_H_ */
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