Annotation of sys/arch/sh/dev/shpcicvar.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: shpcicvar.h,v 1.3 2006/10/19 03:36:38 drahn Exp $ */
2: /* $NetBSD: shpcicvar.h,v 1.6 2005/12/11 12:18:58 christos Exp $ */
3:
4: /*-
5: * Copyright (c) 2005 NONAKA Kimihiro
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: *
17: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27: * SUCH DAMAGE.
28: */
29:
30: #ifndef SH_DEV_PCICVAR_H
31: #define SH_DEV_PCICVAR_H
32:
33: #include <machine/bus.h>
34:
35: bus_space_tag_t shpcic_get_bus_io_tag(void);
36: bus_space_tag_t shpcic_get_bus_mem_tag(void);
37: bus_dma_tag_t shpcic_get_bus_dma_tag(void);
38:
39: int shpcic_bus_maxdevs(void *v, int busno);
40: pcitag_t shpcic_make_tag(void *v, int bus, int device, int function);
41: void shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp);
42: pcireg_t shpcic_conf_read(void *v, pcitag_t tag, int reg);
43: void shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data);
44:
45: int shpcic_set_intr_priority(int intr, int level);
46: void *shpcic_intr_establish(int evtcode, int (*ih_func)(void *), void *ih_arg,
47: const char *ih_name);
48: void shpcic_intr_disestablish(void *ih);
49:
50: struct config_bus_space {
51: u_int32_t bus_base;
52: u_int32_t bus_size;
53: int bus_io;
54: };
55:
56: struct shpcic_softc {
57: struct device s_dev;
58:
59: pci_chipset_tag_t sc_pci_chipset;
60:
61: /* Structures to do bus fixup */
62: int nbogus;
63: struct extent *extent_mem;
64: struct extent *extent_port;
65: struct config_bus_space sc_membus_space;
66: struct config_bus_space sc_iobus_space;
67: };
68:
69: void pci_addr_fixup(void *v, int maxbus);
70:
71: /*
72: * shpcic io/mem bus space
73: */
74: int shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size, int flags,
75: bus_space_handle_t *bshp);
76: void shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size);
77: int shpcic_iomem_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset,
78: bus_size_t size, bus_space_handle_t *nbshp);
79: int shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend,
80: bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
81: bus_addr_t *bpap, bus_space_handle_t *bshp);
82: void shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size);
83:
84: /* read single */
85: uint8_t shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset);
86: uint16_t shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset);
87: uint32_t shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset);
88: uint8_t shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset);
89: uint16_t shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset);
90: uint32_t shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset);
91:
92: /* read multi */
93: void shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh,
94: bus_size_t offset, uint8_t *addr, bus_size_t count);
95: void shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh,
96: bus_size_t offset, uint16_t *addr, bus_size_t count);
97: void shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh,
98: bus_size_t offset, uint32_t *addr, bus_size_t count);
99: void shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh,
100: bus_size_t offset, uint8_t *addr, bus_size_t count);
101: void shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh,
102: bus_size_t offset, uint16_t *addr, bus_size_t count);
103: void shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh,
104: bus_size_t offset, uint32_t *addr, bus_size_t count);
105:
106: /* read raw multi */
107: void shpcic_io_read_raw_multi_2(void *v, bus_space_handle_t bsh,
108: bus_size_t offset, uint8_t *addr, bus_size_t count);
109: void shpcic_io_read_raw_multi_4(void *v, bus_space_handle_t bsh,
110: bus_size_t offset, uint8_t *addr, bus_size_t count);
111: void shpcic_mem_read_raw_multi_2(void *v, bus_space_handle_t bsh,
112: bus_size_t offset, uint8_t *addr, bus_size_t count);
113: void shpcic_mem_read_raw_multi_4(void *v, bus_space_handle_t bsh,
114: bus_size_t offset, uint8_t *addr, bus_size_t count);
115:
116: /* read region */
117: void shpcic_io_read_region_1(void *v, bus_space_handle_t bsh,
118: bus_size_t offset, uint8_t *addr, bus_size_t count);
119: void shpcic_io_read_region_2(void *v, bus_space_handle_t bsh,
120: bus_size_t offset, uint16_t *addr, bus_size_t count);
121: void shpcic_io_read_region_4(void *v, bus_space_handle_t bsh,
122: bus_size_t offset, uint32_t *addr, bus_size_t count);
123: void shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh,
124: bus_size_t offset, uint8_t *addr, bus_size_t count);
125: void shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh,
126: bus_size_t offset, uint16_t *addr, bus_size_t count);
127: void shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh,
128: bus_size_t offset, uint32_t *addr, bus_size_t count);
129:
130: /* read raw region */
131: void shpcic_io_read_raw_region_2(void *v, bus_space_handle_t bsh,
132: bus_size_t offset, uint8_t *addr, bus_size_t count);
133: void shpcic_io_read_raw_region_4(void *v, bus_space_handle_t bsh,
134: bus_size_t offset, uint8_t *addr, bus_size_t count);
135: void shpcic_mem_read_raw_region_2(void *v, bus_space_handle_t bsh,
136: bus_size_t offset, uint8_t *addr, bus_size_t count);
137: void shpcic_mem_read_raw_region_4(void *v, bus_space_handle_t bsh,
138: bus_size_t offset, uint8_t *addr, bus_size_t count);
139:
140: /* write single */
141: void shpcic_io_write_1(void *v, bus_space_handle_t bsh,
142: bus_size_t offset, uint8_t data);
143: void shpcic_io_write_2(void *v, bus_space_handle_t bsh,
144: bus_size_t offset, uint16_t data);
145: void shpcic_io_write_4(void *v, bus_space_handle_t bsh,
146: bus_size_t offset, uint32_t data);
147: void shpcic_mem_write_1(void *v, bus_space_handle_t bsh,
148: bus_size_t offset, uint8_t data);
149: void shpcic_mem_write_2(void *v, bus_space_handle_t bsh,
150: bus_size_t offset, uint16_t data);
151: void shpcic_mem_write_4(void *v, bus_space_handle_t bsh,
152: bus_size_t offset, uint32_t data);
153:
154: /* write multi */
155: void shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh,
156: bus_size_t offset, const uint8_t *addr, bus_size_t count);
157: void shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh,
158: bus_size_t offset, const uint16_t *addr, bus_size_t count);
159: void shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh,
160: bus_size_t offset, const uint32_t *addr, bus_size_t count);
161: void shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh,
162: bus_size_t offset, const uint8_t *addr, bus_size_t count);
163: void shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh,
164: bus_size_t offset, const uint16_t *addr, bus_size_t count);
165: void shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh,
166: bus_size_t offset, const uint32_t *addr, bus_size_t count);
167:
168: /* write raw multi */
169: void shpcic_io_write_raw_multi_2(void *v, bus_space_handle_t bsh,
170: bus_size_t offset, const uint8_t *addr, bus_size_t count);
171: void shpcic_io_write_raw_multi_4(void *v, bus_space_handle_t bsh,
172: bus_size_t offset, const uint8_t *addr, bus_size_t count);
173: void shpcic_mem_write_raw_multi_2(void *v, bus_space_handle_t bsh,
174: bus_size_t offset, const uint8_t *addr, bus_size_t count);
175: void shpcic_mem_write_raw_multi_4(void *v, bus_space_handle_t bsh,
176: bus_size_t offset, const uint8_t *addr, bus_size_t count);
177:
178: /* write region */
179: void shpcic_io_write_region_1(void *v, bus_space_handle_t bsh,
180: bus_size_t offset, const uint8_t *addr, bus_size_t count);
181: void shpcic_io_write_region_2(void *v, bus_space_handle_t bsh,
182: bus_size_t offset, const uint16_t *addr, bus_size_t count);
183: void shpcic_io_write_region_4(void *v, bus_space_handle_t bsh,
184: bus_size_t offset, const uint32_t *addr, bus_size_t count);
185: void shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh,
186: bus_size_t offset, const uint8_t *addr, bus_size_t count);
187: void shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh,
188: bus_size_t offset, const uint16_t *addr, bus_size_t count);
189: void shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh,
190: bus_size_t offset, const uint32_t *addr, bus_size_t count);
191:
192: /* write raw region */
193: void shpcic_io_write_raw_region_2(void *v, bus_space_handle_t bsh,
194: bus_size_t offset, const uint8_t *addr, bus_size_t count);
195: void shpcic_io_write_raw_region_4(void *v, bus_space_handle_t bsh,
196: bus_size_t offset, const uint8_t *addr, bus_size_t count);
197: void shpcic_mem_write_raw_region_2(void *v, bus_space_handle_t bsh,
198: bus_size_t offset, const uint8_t *addr, bus_size_t count);
199: void shpcic_mem_write_raw_region_4(void *v, bus_space_handle_t bsh,
200: bus_size_t offset, const uint8_t *addr, bus_size_t count);
201:
202: /* set multi */
203: void shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh,
204: bus_size_t offset, uint8_t val, bus_size_t count);
205: void shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh,
206: bus_size_t offset, uint16_t val, bus_size_t count);
207: void shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh,
208: bus_size_t offset, uint32_t val, bus_size_t count);
209: void shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh,
210: bus_size_t offset, uint8_t val, bus_size_t count);
211: void shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh,
212: bus_size_t offset, uint16_t val, bus_size_t count);
213: void shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh,
214: bus_size_t offset, uint32_t val, bus_size_t count);
215:
216: /* set region */
217: void shpcic_io_set_region_1(void *v, bus_space_handle_t bsh,
218: bus_size_t offset, uint8_t val, bus_size_t count);
219: void shpcic_io_set_region_2(void *v, bus_space_handle_t bsh,
220: bus_size_t offset, uint16_t val, bus_size_t count);
221: void shpcic_io_set_region_4(void *v, bus_space_handle_t bsh,
222: bus_size_t offset, uint32_t val, bus_size_t count);
223: void shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh,
224: bus_size_t offset, uint8_t val, bus_size_t count);
225: void shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh,
226: bus_size_t offset, uint16_t val, bus_size_t count);
227: void shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh,
228: bus_size_t offset, uint32_t val, bus_size_t count);
229:
230: /* copy region */
231: void shpcic_io_copy_region_1(void *v, bus_space_handle_t bsh1,
232: bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
233: bus_size_t count);
234: void shpcic_io_copy_region_2(void *v, bus_space_handle_t bsh1,
235: bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
236: bus_size_t count);
237: void shpcic_io_copy_region_4(void *v, bus_space_handle_t bsh1,
238: bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
239: bus_size_t count);
240: void shpcic_mem_copy_region_1(void *v, bus_space_handle_t bsh1,
241: bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
242: bus_size_t count);
243: void shpcic_mem_copy_region_2(void *v, bus_space_handle_t bsh1,
244: bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
245: bus_size_t count);
246: void shpcic_mem_copy_region_4(void *v, bus_space_handle_t bsh1,
247: bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2,
248: bus_size_t count);
249: #endif /* SH_DEV_PCICVAR_H */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to shpcicvar.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / arch / sh / dev