Annotation of sys/arch/sh/dev/shpcic.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: shpcic.c,v 1.7 2007/07/11 18:21:35 miod Exp $ */
2: /* $NetBSD: shpcic.c,v 1.10 2005/12/24 20:07:32 perry Exp $ */
3:
4: /*
5: * Copyright (c) 2005 NONAKA Kimihiro
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: *
17: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27: */
28:
29: #include <sys/param.h>
30: #include <sys/systm.h>
31: #include <sys/kernel.h>
32: #include <sys/device.h>
33: #include <sys/extent.h>
34: #include <sys/malloc.h>
35:
36: #include <dev/pci/pcireg.h>
37: #include <dev/pci/pcivar.h>
38: #include <dev/pci/pcidevs.h>
39:
40: #include <sh/bscreg.h>
41: #include <sh/cache.h>
42: #include <sh/trap.h>
43: #include <sh/dev/pcicreg.h>
44:
45: #include <machine/autoconf.h>
46: #include <machine/bus.h>
47: #include <machine/intr.h>
48:
49: #if defined(SHPCIC_DEBUG)
50: int shpcic_debug = 0;
51: #define DPRINTF(arg) if (shpcic_debug) printf arg
52: #else
53: #define DPRINTF(arg)
54: #endif
55:
56: #define PCI_MODE1_ENABLE 0x80000000UL
57:
58: static const struct shpcic_product {
59: uint32_t sp_product;
60: const char *sp_name;
61: } shpcic_products[] = {
62: { PCI_PRODUCT_HITACHI_SH7751, "SH7751" },
63: { PCI_PRODUCT_HITACHI_SH7751R, "SH7751R" },
64:
65: { 0, NULL },
66: };
67:
68: int shpcic_match(struct device *, void *, void *);
69: void shpcic_attach(struct device *, struct device *, void *);
70:
71: struct cfattach shpcic_ca = {
72: sizeof(struct shpcic_softc), shpcic_match, shpcic_attach
73: };
74:
75: struct cfdriver shpcic_cd = {
76: 0, "shpcic", DV_DULL
77: };
78:
79: /* There can be only one. */
80: int shpcic_found = 0;
81:
82: static const struct shpcic_product *shpcic_lookup(void);
83:
84: static const struct shpcic_product *
85: shpcic_lookup(void)
86: {
87: const struct shpcic_product *spp;
88: pcireg_t id;
89:
90: id = _reg_read_4(SH4_PCICONF0);
91: switch (PCI_VENDOR(id)) {
92: case PCI_VENDOR_HITACHI:
93: break;
94:
95: default:
96: return (NULL);
97: }
98:
99: for (spp = shpcic_products; spp->sp_name != NULL; spp++) {
100: if (PCI_PRODUCT(id) == spp->sp_product) {
101: return (spp);
102: }
103: }
104: return (NULL);
105: }
106:
107: int
108: shpcic_match(struct device *parent, void *vcf, void *aux)
109: {
110: struct mainbus_attach_args *ma = aux;
111:
112: if (strcmp(ma->ma_name, shpcic_cd.cd_name) != 0)
113: return (0);
114:
115: if (!CPU_IS_SH4)
116: return (0);
117:
118: switch (cpu_product) {
119: default:
120: return (0);
121:
122: case CPU_PRODUCT_7751:
123: case CPU_PRODUCT_7751R:
124: break;
125: }
126:
127: if (shpcic_found)
128: return (0);
129:
130: if (shpcic_lookup() == NULL)
131: return (0);
132:
133: if (_reg_read_2(SH4_BCR2) & BCR2_PORTEN)
134: return (0);
135:
136: return (1);
137: }
138:
139: void
140: shpcic_attach(struct device *parent, struct device *self, void *aux)
141: {
142: const struct shpcic_product *spp;
143: struct shpcic_softc *sc = (struct shpcic_softc *)self;
144: struct pcibus_attach_args pba;
145:
146: shpcic_found = 1;
147:
148: spp = shpcic_lookup();
149: if (spp == NULL) {
150: printf("\n");
151: panic("shpcic_attach: impossible");
152: }
153:
154: if (_reg_read_2(SH4_BCR2) & BCR2_PORTEN) {
155: printf("\n");
156: panic("shpcic_attach: port enabled");
157: }
158:
159: printf(": HITACHI %s\n", spp->sp_name);
160:
161: /* allow PCIC request */
162: _reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);
163:
164: /* Initialize PCIC */
165: _reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_RSTCTL);
166: delay(10 * 1000);
167: _reg_write_4(SH4_PCICR, PCICR_BASE);
168:
169: /* Class: Host-Bridge */
170: _reg_write_4(SH4_PCICONF2,
171: (PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT) |
172: (PCI_SUBCLASS_BRIDGE_HOST << PCI_SUBCLASS_SHIFT));
173:
174: #if !defined(DONT_INIT_PCIBSC)
175: #if defined(PCIBCR_BCR1_VAL)
176: _reg_write_4(SH4_PCIBCR1, PCIBCR_BCR1_VAL);
177: #else
178: _reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);
179: #endif
180: #if defined(PCIBCR_BCR2_VAL)
181: _reg_write_4(SH4_PCIBCR2, PCIBCR_BCR2_VAL);
182: #else
183: _reg_write_4(SH4_PCIBCR2, _reg_read_2(SH4_BCR2));
184: #endif
185: #if defined(SH4) && defined(SH7751R)
186: if (cpu_product == CPU_PRODUCT_7751R) {
187: #if defined(PCIBCR_BCR3_VAL)
188: _reg_write_4(SH4_PCIBCR3, PCIBCR_BCR3_VAL);
189: #else
190: _reg_write_4(SH4_PCIBCR3, _reg_read_2(SH4_BCR3));
191: #endif
192: }
193: #endif /* SH4 && SH7751R && PCIBCR_BCR3_VAL */
194: #if defined(PCIBCR_WCR1_VAL)
195: _reg_write_4(SH4_PCIWCR1, PCIBCR_WCR1_VAL);
196: #else
197: _reg_write_4(SH4_PCIWCR1, _reg_read_4(SH4_WCR1));
198: #endif
199: #if defined(PCIBCR_WCR2_VAL)
200: _reg_write_4(SH4_PCIWCR2, PCIBCR_WCR2_VAL);
201: #else
202: _reg_write_4(SH4_PCIWCR2, _reg_read_4(SH4_WCR2));
203: #endif
204: #if defined(PCIBCR_WCR3_VAL)
205: _reg_write_4(SH4_PCIWCR3, PCIBCR_WCR3_VAL);
206: #else
207: _reg_write_4(SH4_PCIWCR3, _reg_read_4(SH4_WCR3));
208: #endif
209: #if defined(PCIBCR_MCR_VAL)
210: _reg_write_4(SH4_PCIMCR, PCIBCR_MCR_VAL);
211: #else
212: _reg_write_4(SH4_PCIMCR, _reg_read_4(SH4_MCR));
213: #endif
214: #endif /* !DONT_INIT_PCIBSC */
215:
216: /* set PCI I/O, memory base address */
217: _reg_write_4(SH4_PCIIOBR, SH4_PCIC_IO);
218: _reg_write_4(SH4_PCIMBR, SH4_PCIC_MEM);
219:
220: /* set PCI local address 0 */
221: _reg_write_4(SH4_PCILSR0, (64 - 1) << 20);
222: _reg_write_4(SH4_PCILAR0, 0xac000000);
223: _reg_write_4(SH4_PCICONF5, 0xac000000);
224:
225: /* set PCI local address 1 */
226: _reg_write_4(SH4_PCILSR1, (64 - 1) << 20);
227: _reg_write_4(SH4_PCILAR1, 0xac000000);
228: _reg_write_4(SH4_PCICONF6, 0x8c000000);
229:
230: /* Enable I/O, memory, bus-master */
231: _reg_write_4(SH4_PCICONF1, PCI_COMMAND_IO_ENABLE
232: | PCI_COMMAND_MEM_ENABLE
233: | PCI_COMMAND_MASTER_ENABLE
234: | PCI_COMMAND_STEPPING_ENABLE
235: | PCI_STATUS_DEVSEL_MEDIUM);
236:
237: /* Initialize done. */
238: _reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_CFINIT);
239:
240: /* set PCI controller interrupt priority */
241: intpri_intr_priority(SH4_INTEVT_PCIERR, IPL_BIO); /* IPL_HIGH? */
242: intpri_intr_priority(SH4_INTEVT_PCISERR, IPL_BIO); /* IPL_HIGH? */
243:
244: sc->sc_membus_space.bus_base = SH4_PCIC_MEM;
245: sc->sc_membus_space.bus_size = SH4_PCIC_MEM_SIZE;
246: sc->sc_membus_space.bus_io = 0;
247: sc->sc_iobus_space.bus_base = SH4_PCIC_IO; /* XXX */
248: sc->sc_iobus_space.bus_size = SH4_PCIC_IO_SIZE;
249: sc->sc_iobus_space.bus_io = 1;;
250:
251: sc->sc_pci_chipset = shpcic_get_bus_mem_tag();
252: pci_addr_fixup(sc, 1);
253:
254: /* PCI bus */
255: memset(&pba, 0, sizeof(pba));
256: pba.pba_busname = "pci";
257: pba.pba_iot = shpcic_get_bus_io_tag();
258: pba.pba_memt = shpcic_get_bus_mem_tag();
259: pba.pba_dmat = shpcic_get_bus_dma_tag();
260: pba.pba_pc = NULL;
261: pba.pba_domain = pci_ndomains++;
262: pba.pba_bus = 0;
263: pba.pba_bridgetag = NULL;
264: config_found(self, &pba, NULL);
265: }
266:
267: int
268: shpcic_bus_maxdevs(void *v, int busno)
269: {
270: /*
271: * Bus number is irrelevant. Configuration Mechanism 1 is in
272: * use, can have devices 0-32 (i.e. the `normal' range).
273: */
274: return (32);
275: }
276:
277: pcitag_t
278: shpcic_make_tag(void *v, int bus, int device, int function)
279: {
280: pcitag_t tag;
281:
282: if (bus >= 256 || device >= 32 || function >= 8)
283: panic("pci_make_tag: bad request");
284:
285: tag = PCI_MODE1_ENABLE |
286: (bus << 16) | (device << 11) | (function << 8);
287:
288: return (tag);
289: }
290:
291: void
292: shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
293: {
294: if (bp != NULL)
295: *bp = (tag >> 16) & 0xff;
296: if (dp != NULL)
297: *dp = (tag >> 11) & 0x1f;
298: if (fp != NULL)
299: *fp = (tag >> 8) & 0x7;
300: }
301:
302: pcireg_t
303: shpcic_conf_read(void *v, pcitag_t tag, int reg)
304: {
305: pcireg_t data;
306: int s;
307:
308: s = splhigh();
309: _reg_write_4(SH4_PCIPAR, tag | reg);
310: data = _reg_read_4(SH4_PCIPDR);
311: _reg_write_4(SH4_PCIPAR, 0);
312: splx(s);
313:
314: return data;
315: }
316:
317: void
318: shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
319: {
320: int s;
321:
322: s = splhigh();
323: _reg_write_4(SH4_PCIPAR, tag | reg);
324: _reg_write_4(SH4_PCIPDR, data);
325: _reg_write_4(SH4_PCIPAR, 0);
326: splx(s);
327: }
328:
329: /*
330: * shpcic bus space
331: */
332: int
333: shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size,
334: int flags, bus_space_handle_t *bshp)
335: {
336: *bshp = (bus_space_handle_t)bpa;
337:
338: return (0);
339: }
340:
341: void
342: shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size)
343: {
344: /* Nothing to do */
345: }
346:
347: int
348: shpcic_iomem_subregion(void *v, bus_space_handle_t bsh,
349: bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp)
350: {
351: *nbshp = bsh + offset;
352:
353: return (0);
354: }
355:
356: int
357: shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend,
358: bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
359: bus_addr_t *bpap, bus_space_handle_t *bshp)
360: {
361: *bshp = *bpap = rstart;
362:
363: return (0);
364: }
365:
366: void
367: shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size)
368: {
369: /* Nothing to do */
370: }
371:
372: /*
373: * shpcic bus space io/mem read/write
374: */
375: /* read */
376: static inline uint8_t __shpcic_io_read_1(bus_space_handle_t bsh,
377: bus_size_t offset);
378: static inline uint16_t __shpcic_io_read_2(bus_space_handle_t bsh,
379: bus_size_t offset);
380: static inline uint32_t __shpcic_io_read_4(bus_space_handle_t bsh,
381: bus_size_t offset);
382: static inline uint8_t __shpcic_mem_read_1(bus_space_handle_t bsh,
383: bus_size_t offset);
384: static inline uint16_t __shpcic_mem_read_2(bus_space_handle_t bsh,
385: bus_size_t offset);
386: static inline uint32_t __shpcic_mem_read_4(bus_space_handle_t bsh,
387: bus_size_t offset);
388:
389: static inline uint8_t
390: __shpcic_io_read_1(bus_space_handle_t bsh, bus_size_t offset)
391: {
392: u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;
393:
394: return *(volatile uint8_t *)(SH4_PCIC_IO + adr);
395: }
396:
397: static inline uint16_t
398: __shpcic_io_read_2(bus_space_handle_t bsh, bus_size_t offset)
399: {
400: u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;
401:
402: return *(volatile uint16_t *)(SH4_PCIC_IO + adr);
403: }
404:
405: static inline uint32_t
406: __shpcic_io_read_4(bus_space_handle_t bsh, bus_size_t offset)
407: {
408: u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;
409:
410: return *(volatile uint32_t *)(SH4_PCIC_IO + adr);
411: }
412:
413: static inline uint8_t
414: __shpcic_mem_read_1(bus_space_handle_t bsh, bus_size_t offset)
415: {
416: u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;
417:
418: return *(volatile uint8_t *)(SH4_PCIC_MEM + adr);
419: }
420:
421: static inline uint16_t
422: __shpcic_mem_read_2(bus_space_handle_t bsh, bus_size_t offset)
423: {
424: u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;
425:
426: return *(volatile uint16_t *)(SH4_PCIC_MEM + adr);
427: }
428:
429: static inline uint32_t
430: __shpcic_mem_read_4(bus_space_handle_t bsh, bus_size_t offset)
431: {
432: u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;
433:
434: return *(volatile uint32_t *)(SH4_PCIC_MEM + adr);
435: }
436:
437: /*
438: * read single
439: */
440: uint8_t
441: shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset)
442: {
443: uint8_t value;
444:
445: value = __shpcic_io_read_1(bsh, offset);
446:
447: return value;
448: }
449:
450: uint16_t
451: shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset)
452: {
453: uint16_t value;
454:
455: value = __shpcic_io_read_2(bsh, offset);
456:
457: return value;
458: }
459:
460: uint32_t
461: shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset)
462: {
463: uint32_t value;
464:
465: value = __shpcic_io_read_4(bsh, offset);
466:
467: return value;
468: }
469:
470: uint8_t
471: shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset)
472: {
473: uint8_t value;
474:
475: value = __shpcic_mem_read_1(bsh, offset);
476:
477: return value;
478: }
479:
480: uint16_t
481: shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset)
482: {
483: uint16_t value;
484:
485: value = __shpcic_mem_read_2(bsh, offset);
486:
487: return value;
488: }
489:
490: uint32_t
491: shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset)
492: {
493: uint32_t value;
494:
495: value = __shpcic_mem_read_4(bsh, offset);
496:
497: return value;
498: }
499:
500: /*
501: * read multi
502: */
503: void
504: shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh,
505: bus_size_t offset, uint8_t *addr, bus_size_t count)
506: {
507: while (count--) {
508: *addr++ = __shpcic_io_read_1(bsh, offset);
509: }
510: }
511:
512: void
513: shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh,
514: bus_size_t offset, uint16_t *addr, bus_size_t count)
515: {
516: while (count--) {
517: *addr++ = __shpcic_io_read_2(bsh, offset);
518: }
519: }
520:
521: void
522: shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh,
523: bus_size_t offset, uint32_t *addr, bus_size_t count)
524: {
525: while (count--) {
526: *addr++ = __shpcic_io_read_4(bsh, offset);
527: }
528: }
529:
530: void
531: shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh,
532: bus_size_t offset, uint8_t *addr, bus_size_t count)
533: {
534: while (count--) {
535: *addr++ = __shpcic_mem_read_1(bsh, offset);
536: }
537: }
538:
539: void
540: shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh,
541: bus_size_t offset, uint16_t *addr, bus_size_t count)
542: {
543: while (count--) {
544: *addr++ = __shpcic_mem_read_2(bsh, offset);
545: }
546: }
547:
548: void
549: shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh,
550: bus_size_t offset, uint32_t *addr, bus_size_t count)
551: {
552: while (count--) {
553: *addr++ = __shpcic_mem_read_4(bsh, offset);
554: }
555: }
556:
557: /*
558: * read raw multi
559: */
560:
561: void
562: shpcic_io_read_raw_multi_2(void *v, bus_space_handle_t bsh,
563: bus_size_t offset, uint8_t *addr, bus_size_t count)
564: {
565: count >>= 1;
566: while (count--) {
567: *(uint16_t *)addr = __shpcic_io_read_2(bsh, offset);
568: addr += 2;
569: }
570: }
571:
572: void
573: shpcic_io_read_raw_multi_4(void *v, bus_space_handle_t bsh,
574: bus_size_t offset, uint8_t *addr, bus_size_t count)
575: {
576: count >>= 2;
577: while (count--) {
578: *(uint32_t *)addr = __shpcic_io_read_4(bsh, offset);
579: addr += 4;
580: }
581: }
582:
583: void
584: shpcic_mem_read_raw_multi_2(void *v, bus_space_handle_t bsh,
585: bus_size_t offset, uint8_t *addr, bus_size_t count)
586: {
587: count >>= 1;
588: while (count--) {
589: *(uint16_t *)addr = __shpcic_mem_read_2(bsh, offset);
590: addr += 2;
591: }
592: }
593:
594: void
595: shpcic_mem_read_raw_multi_4(void *v, bus_space_handle_t bsh,
596: bus_size_t offset, uint8_t *addr, bus_size_t count)
597: {
598: count >>= 2;
599: while (count--) {
600: *(uint32_t *)addr = __shpcic_mem_read_4(bsh, offset);
601: addr += 4;
602: }
603: }
604:
605: /*
606: * read region
607: */
608: void
609: shpcic_io_read_region_1(void *v, bus_space_handle_t bsh,
610: bus_size_t offset, uint8_t *addr, bus_size_t count)
611: {
612: while (count--) {
613: *addr++ = __shpcic_io_read_1(bsh, offset);
614: offset += 1;
615: }
616: }
617:
618: void
619: shpcic_io_read_region_2(void *v, bus_space_handle_t bsh,
620: bus_size_t offset, uint16_t *addr, bus_size_t count)
621: {
622: while (count--) {
623: *addr++ = __shpcic_io_read_2(bsh, offset);
624: offset += 2;
625: }
626: }
627:
628: void
629: shpcic_io_read_region_4(void *v, bus_space_handle_t bsh,
630: bus_size_t offset, uint32_t *addr, bus_size_t count)
631: {
632: while (count--) {
633: *addr++ = __shpcic_io_read_4(bsh, offset);
634: offset += 4;
635: }
636: }
637:
638: void
639: shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh,
640: bus_size_t offset, uint8_t *addr, bus_size_t count)
641: {
642: while (count--) {
643: *addr++ = __shpcic_mem_read_1(bsh, offset);
644: offset += 1;
645: }
646: }
647:
648: void
649: shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh,
650: bus_size_t offset, uint16_t *addr, bus_size_t count)
651: {
652: while (count--) {
653: *addr++ = __shpcic_mem_read_2(bsh, offset);
654: offset += 2;
655: }
656: }
657:
658: void
659: shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh,
660: bus_size_t offset, uint32_t *addr, bus_size_t count)
661: {
662: while (count--) {
663: *addr++ = __shpcic_mem_read_4(bsh, offset);
664: offset += 4;
665: }
666: }
667:
668: /*
669: * read raw region
670: */
671:
672: void
673: shpcic_io_read_raw_region_2(void *v, bus_space_handle_t bsh,
674: bus_size_t offset, uint8_t *addr, bus_size_t count)
675: {
676: count >>= 1;
677: while (count--) {
678: *(uint16_t *)addr = __shpcic_io_read_2(bsh, offset);
679: addr += 2;
680: offset += 2;
681: }
682: }
683:
684: void
685: shpcic_io_read_raw_region_4(void *v, bus_space_handle_t bsh,
686: bus_size_t offset, uint8_t *addr, bus_size_t count)
687: {
688: count >>= 2;
689: while (count--) {
690: *(uint32_t *)addr = __shpcic_io_read_4(bsh, offset);
691: addr += 4;
692: offset += 4;
693: }
694: }
695:
696: void
697: shpcic_mem_read_raw_region_2(void *v, bus_space_handle_t bsh,
698: bus_size_t offset, uint8_t *addr, bus_size_t count)
699: {
700: count >>= 1;
701: while (count--) {
702: *(uint16_t *)addr = __shpcic_mem_read_2(bsh, offset);
703: addr += 2;
704: offset += 2;
705: }
706: }
707:
708: void
709: shpcic_mem_read_raw_region_4(void *v, bus_space_handle_t bsh,
710: bus_size_t offset, uint8_t *addr, bus_size_t count)
711: {
712: count >>= 2;
713: while (count--) {
714: *(uint32_t *)addr = __shpcic_mem_read_4(bsh, offset);
715: addr += 4;
716: offset += 4;
717: }
718: }
719:
720: /* write */
721: static inline void __shpcic_io_write_1(bus_space_handle_t bsh,
722: bus_size_t offset, uint8_t value);
723: static inline void __shpcic_io_write_2(bus_space_handle_t bsh,
724: bus_size_t offset, uint16_t value);
725: static inline void __shpcic_io_write_4(bus_space_handle_t bsh,
726: bus_size_t offset, uint32_t value);
727: static inline void __shpcic_mem_write_1(bus_space_handle_t bsh,
728: bus_size_t offset, uint8_t value);
729: static inline void __shpcic_mem_write_2(bus_space_handle_t bsh,
730: bus_size_t offset, uint16_t value);
731: static inline void __shpcic_mem_write_4(bus_space_handle_t bsh,
732: bus_size_t offset, uint32_t value);
733:
734: static inline void
735: __shpcic_io_write_1(bus_space_handle_t bsh, bus_size_t offset,
736: uint8_t value)
737: {
738: u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;
739:
740: *(volatile uint8_t *)(SH4_PCIC_IO + adr) = value;
741: }
742:
743: static inline void
744: __shpcic_io_write_2(bus_space_handle_t bsh, bus_size_t offset,
745: uint16_t value)
746: {
747: u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;
748:
749: *(volatile uint16_t *)(SH4_PCIC_IO + adr) = value;
750: }
751:
752: static inline void
753: __shpcic_io_write_4(bus_space_handle_t bsh, bus_size_t offset,
754: uint32_t value)
755: {
756: u_long adr = (u_long)(bsh + offset) & SH4_PCIC_IO_MASK;
757:
758: *(volatile uint32_t *)(SH4_PCIC_IO + adr) = value;
759: }
760:
761: static inline void
762: __shpcic_mem_write_1(bus_space_handle_t bsh, bus_size_t offset,
763: uint8_t value)
764: {
765: u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;
766:
767: *(volatile uint8_t *)(SH4_PCIC_MEM + adr) = value;
768: }
769:
770: static inline void
771: __shpcic_mem_write_2(bus_space_handle_t bsh, bus_size_t offset,
772: uint16_t value)
773: {
774: u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;
775:
776: *(volatile uint16_t *)(SH4_PCIC_MEM + adr) = value;
777: }
778:
779: static inline void
780: __shpcic_mem_write_4(bus_space_handle_t bsh, bus_size_t offset,
781: uint32_t value)
782: {
783: u_long adr = (u_long)(bsh + offset) & SH4_PCIC_MEM_MASK;
784:
785: *(volatile uint32_t *)(SH4_PCIC_MEM + adr) = value;
786: }
787:
788: /*
789: * write single
790: */
791: void
792: shpcic_io_write_1(void *v, bus_space_handle_t bsh,
793: bus_size_t offset, uint8_t value)
794: {
795: __shpcic_io_write_1(bsh, offset, value);
796: }
797:
798: void
799: shpcic_io_write_2(void *v, bus_space_handle_t bsh,
800: bus_size_t offset, uint16_t value)
801: {
802: __shpcic_io_write_2(bsh, offset, value);
803: }
804:
805: void
806: shpcic_io_write_4(void *v, bus_space_handle_t bsh,
807: bus_size_t offset, uint32_t value)
808: {
809: __shpcic_io_write_4(bsh, offset, value);
810: }
811:
812: void
813: shpcic_mem_write_1(void *v, bus_space_handle_t bsh,
814: bus_size_t offset, uint8_t value)
815: {
816: __shpcic_mem_write_1(bsh, offset, value);
817: }
818:
819: void
820: shpcic_mem_write_2(void *v, bus_space_handle_t bsh,
821: bus_size_t offset, uint16_t value)
822: {
823: __shpcic_mem_write_2(bsh, offset, value);
824: }
825:
826: void
827: shpcic_mem_write_4(void *v, bus_space_handle_t bsh,
828: bus_size_t offset, uint32_t value)
829: {
830: __shpcic_mem_write_4(bsh, offset, value);
831: }
832:
833: /*
834: * write multi
835: */
836: void
837: shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh,
838: bus_size_t offset, const uint8_t *addr, bus_size_t count)
839: {
840: while (count--) {
841: __shpcic_io_write_1(bsh, offset, *addr++);
842: }
843: }
844:
845: void
846: shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh,
847: bus_size_t offset, const uint16_t *addr, bus_size_t count)
848: {
849: while (count--) {
850: __shpcic_io_write_2(bsh, offset, *addr++);
851: }
852: }
853:
854: void
855: shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh,
856: bus_size_t offset, const uint32_t *addr, bus_size_t count)
857: {
858: while (count--) {
859: __shpcic_io_write_4(bsh, offset, *addr++);
860: }
861: }
862:
863: void
864: shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh,
865: bus_size_t offset, const uint8_t *addr, bus_size_t count)
866: {
867: while (count--) {
868: __shpcic_mem_write_1(bsh, offset, *addr++);
869: }
870: }
871:
872: void
873: shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh,
874: bus_size_t offset, const uint16_t *addr, bus_size_t count)
875: {
876: while (count--) {
877: __shpcic_mem_write_2(bsh, offset, *addr++);
878: }
879: }
880:
881: void
882: shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh,
883: bus_size_t offset, const uint32_t *addr, bus_size_t count)
884: {
885: while (count--) {
886: __shpcic_mem_write_4(bsh, offset, *addr++);
887: }
888: }
889:
890: /*
891: * write raw multi
892: */
893:
894: void
895: shpcic_io_write_raw_multi_2(void *v, bus_space_handle_t bsh,
896: bus_size_t offset, const uint8_t *addr, bus_size_t count)
897: {
898: count >>= 1;
899: while (count--) {
900: __shpcic_io_write_2(bsh, offset, *(uint16_t *)addr);
901: addr += 2;
902: }
903: }
904:
905: void
906: shpcic_io_write_raw_multi_4(void *v, bus_space_handle_t bsh,
907: bus_size_t offset, const uint8_t *addr, bus_size_t count)
908: {
909: count >>= 2;
910: while (count--) {
911: __shpcic_io_write_4(bsh, offset, *(uint32_t *)addr);
912: addr += 4;
913: }
914: }
915:
916: void
917: shpcic_mem_write_raw_multi_2(void *v, bus_space_handle_t bsh,
918: bus_size_t offset, const uint8_t *addr, bus_size_t count)
919: {
920: count >>= 1;
921: while (count--) {
922: __shpcic_mem_write_2(bsh, offset, *(uint16_t *)addr);
923: addr += 2;
924: }
925: }
926:
927: void
928: shpcic_mem_write_raw_multi_4(void *v, bus_space_handle_t bsh,
929: bus_size_t offset, const uint8_t *addr, bus_size_t count)
930: {
931: count >>= 2;
932: while (count--) {
933: __shpcic_mem_write_4(bsh, offset, *(uint32_t *)addr);
934: addr += 4;
935: }
936: }
937:
938: /*
939: * write region
940: */
941: void
942: shpcic_io_write_region_1(void *v, bus_space_handle_t bsh,
943: bus_size_t offset, const uint8_t *addr, bus_size_t count)
944: {
945: while (count--) {
946: __shpcic_io_write_1(bsh, offset, *addr++);
947: offset += 1;
948: }
949: }
950:
951: void
952: shpcic_io_write_region_2(void *v, bus_space_handle_t bsh,
953: bus_size_t offset, const uint16_t *addr, bus_size_t count)
954: {
955: while (count--) {
956: __shpcic_io_write_2(bsh, offset, *addr++);
957: offset += 2;
958: }
959: }
960:
961: void
962: shpcic_io_write_region_4(void *v, bus_space_handle_t bsh,
963: bus_size_t offset, const uint32_t *addr, bus_size_t count)
964: {
965: while (count--) {
966: __shpcic_io_write_4(bsh, offset, *addr++);
967: offset += 4;
968: }
969: }
970:
971: void
972: shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh,
973: bus_size_t offset, const uint8_t *addr, bus_size_t count)
974: {
975: while (count--) {
976: __shpcic_mem_write_1(bsh, offset, *addr++);
977: offset += 1;
978: }
979: }
980:
981: void
982: shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh,
983: bus_size_t offset, const uint16_t *addr, bus_size_t count)
984: {
985: while (count--) {
986: __shpcic_mem_write_2(bsh, offset, *addr++);
987: offset += 2;
988: }
989: }
990:
991: void
992: shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh,
993: bus_size_t offset, const uint32_t *addr, bus_size_t count)
994: {
995: while (count--) {
996: __shpcic_mem_write_4(bsh, offset, *addr++);
997: offset += 4;
998: }
999: }
1000:
1001: /*
1002: * write raw region
1003: */
1004:
1005: void
1006: shpcic_io_write_raw_region_2(void *v, bus_space_handle_t bsh,
1007: bus_size_t offset, const uint8_t *addr, bus_size_t count)
1008: {
1009: count >>= 1;
1010: while (count--) {
1011: __shpcic_io_write_2(bsh, offset, *(uint16_t *)addr);
1012: addr += 2;
1013: offset += 2;
1014: }
1015: }
1016:
1017: void
1018: shpcic_io_write_raw_region_4(void *v, bus_space_handle_t bsh,
1019: bus_size_t offset, const uint8_t *addr, bus_size_t count)
1020: {
1021: count >>= 1;
1022: while (count--) {
1023: __shpcic_io_write_4(bsh, offset, *(uint32_t *)addr);
1024: addr += 4;
1025: offset += 4;
1026: }
1027: }
1028:
1029: void
1030: shpcic_mem_write_raw_region_2(void *v, bus_space_handle_t bsh,
1031: bus_size_t offset, const uint8_t *addr, bus_size_t count)
1032: {
1033: count >>= 1;
1034: while (count--) {
1035: __shpcic_mem_write_2(bsh, offset, *(uint16_t *)addr);
1036: addr += 2;
1037: offset += 2;
1038: }
1039: }
1040:
1041: void
1042: shpcic_mem_write_raw_region_4(void *v, bus_space_handle_t bsh,
1043: bus_size_t offset, const uint8_t *addr, bus_size_t count)
1044: {
1045: count >>= 2;
1046: while (count--) {
1047: __shpcic_mem_write_4(bsh, offset, *(uint32_t *)addr);
1048: addr += 4;
1049: offset += 4;
1050: }
1051: }
1052:
1053: /*
1054: * set multi
1055: */
1056: void
1057: shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh,
1058: bus_size_t offset, uint8_t value, bus_size_t count)
1059: {
1060: while (count--) {
1061: __shpcic_io_write_1(bsh, offset, value);
1062: }
1063: }
1064:
1065: void
1066: shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh,
1067: bus_size_t offset, uint16_t value, bus_size_t count)
1068: {
1069: while (count--) {
1070: __shpcic_io_write_2(bsh, offset, value);
1071: }
1072: }
1073:
1074: void
1075: shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh,
1076: bus_size_t offset, uint32_t value, bus_size_t count)
1077: {
1078: while (count--) {
1079: __shpcic_io_write_4(bsh, offset, value);
1080: }
1081: }
1082:
1083: void
1084: shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh,
1085: bus_size_t offset, uint8_t value, bus_size_t count)
1086: {
1087: while (count--) {
1088: __shpcic_mem_write_1(bsh, offset, value);
1089: }
1090: }
1091:
1092: void
1093: shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh,
1094: bus_size_t offset, uint16_t value, bus_size_t count)
1095: {
1096: while (count--) {
1097: __shpcic_mem_write_2(bsh, offset, value);
1098: }
1099: }
1100:
1101: void
1102: shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh,
1103: bus_size_t offset, uint32_t value, bus_size_t count)
1104: {
1105: while (count--) {
1106: __shpcic_mem_write_4(bsh, offset, value);
1107: }
1108: }
1109:
1110: /*
1111: * set region
1112: */
1113: void
1114: shpcic_io_set_region_1(void *v, bus_space_handle_t bsh,
1115: bus_size_t offset, uint8_t value, bus_size_t count)
1116: {
1117: while (count--) {
1118: __shpcic_io_write_1(bsh, offset, value);
1119: offset += 1;
1120: }
1121: }
1122:
1123: void
1124: shpcic_io_set_region_2(void *v, bus_space_handle_t bsh,
1125: bus_size_t offset, uint16_t value, bus_size_t count)
1126: {
1127: while (count--) {
1128: __shpcic_io_write_2(bsh, offset, value);
1129: offset += 2;
1130: }
1131: }
1132:
1133: void
1134: shpcic_io_set_region_4(void *v, bus_space_handle_t bsh,
1135: bus_size_t offset, uint32_t value, bus_size_t count)
1136: {
1137: while (count--) {
1138: __shpcic_io_write_4(bsh, offset, value);
1139: offset += 4;
1140: }
1141: }
1142:
1143: void
1144: shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh,
1145: bus_size_t offset, uint8_t value, bus_size_t count)
1146: {
1147: while (count--) {
1148: __shpcic_mem_write_1(bsh, offset, value);
1149: offset += 1;
1150: }
1151: }
1152:
1153: void
1154: shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh,
1155: bus_size_t offset, uint16_t value, bus_size_t count)
1156: {
1157: while (count--) {
1158: __shpcic_mem_write_2(bsh, offset, value);
1159: offset += 2;
1160: }
1161: }
1162:
1163: void
1164: shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh,
1165: bus_size_t offset, uint32_t value, bus_size_t count)
1166: {
1167: while (count--) {
1168: __shpcic_mem_write_4(bsh, offset, value);
1169: offset += 4;
1170: }
1171: }
1172:
1173: /*
1174: * copy region
1175: */
1176: void
1177: shpcic_io_copy_region_1(void *v, bus_space_handle_t bsh1,
1178: bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
1179: {
1180: u_long addr1 = bsh1 + off1;
1181: u_long addr2 = bsh2 + off2;
1182: uint8_t value;
1183:
1184: if (addr1 >= addr2) { /* src after dest: copy forward */
1185: while (count--) {
1186: value = __shpcic_io_read_1(bsh1, off1);
1187: __shpcic_io_write_1(bsh2, off2, value);
1188: off1 += 1;
1189: off2 += 1;
1190: }
1191: } else { /* dest after src: copy backwards */
1192: off1 += (count - 1) * 1;
1193: off2 += (count - 1) * 1;
1194: while (count--) {
1195: value = __shpcic_io_read_1(bsh1, off1);
1196: __shpcic_io_write_1(bsh2, off2, value);
1197: off1 -= 1;
1198: off2 -= 1;
1199: }
1200: }
1201: }
1202:
1203: void
1204: shpcic_io_copy_region_2(void *v, bus_space_handle_t bsh1,
1205: bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
1206: {
1207: u_long addr1 = bsh1 + off1;
1208: u_long addr2 = bsh2 + off2;
1209: uint16_t value;
1210:
1211: if (addr1 >= addr2) { /* src after dest: copy forward */
1212: while (count--) {
1213: value = __shpcic_io_read_2(bsh1, off1);
1214: __shpcic_io_write_2(bsh2, off2, value);
1215: off1 += 2;
1216: off2 += 2;
1217: }
1218: } else { /* dest after src: copy backwards */
1219: off1 += (count - 1) * 2;
1220: off2 += (count - 1) * 2;
1221: while (count--) {
1222: value = __shpcic_io_read_2(bsh1, off1);
1223: __shpcic_io_write_2(bsh2, off2, value);
1224: off1 -= 2;
1225: off2 -= 2;
1226: }
1227: }
1228: }
1229:
1230: void
1231: shpcic_io_copy_region_4(void *v, bus_space_handle_t bsh1,
1232: bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
1233: {
1234: u_long addr1 = bsh1 + off1;
1235: u_long addr2 = bsh2 + off2;
1236: uint32_t value;
1237:
1238: if (addr1 >= addr2) { /* src after dest: copy forward */
1239: while (count--) {
1240: value = __shpcic_io_read_4(bsh1, off1);
1241: __shpcic_io_write_4(bsh2, off2, value);
1242: off1 += 4;
1243: off2 += 4;
1244: }
1245: } else { /* dest after src: copy backwards */
1246: off1 += (count - 1) * 4;
1247: off2 += (count - 1) * 4;
1248: while (count--) {
1249: value = __shpcic_io_read_4(bsh1, off1);
1250: __shpcic_io_write_4(bsh2, off2, value);
1251: off1 -= 4;
1252: off2 -= 4;
1253: }
1254: }
1255: }
1256:
1257: void
1258: shpcic_mem_copy_region_1(void *v, bus_space_handle_t bsh1,
1259: bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
1260: {
1261: u_long addr1 = bsh1 + off1;
1262: u_long addr2 = bsh2 + off2;
1263: uint8_t value;
1264:
1265: if (addr1 >= addr2) { /* src after dest: copy forward */
1266: while (count--) {
1267: value = __shpcic_mem_read_1(bsh1, off1);
1268: __shpcic_mem_write_1(bsh2, off2, value);
1269: off1 += 1;
1270: off2 += 1;
1271: }
1272: } else { /* dest after src: copy backwards */
1273: off1 += (count - 1) * 1;
1274: off2 += (count - 1) * 1;
1275: while (count--) {
1276: value = __shpcic_mem_read_1(bsh1, off1);
1277: __shpcic_mem_write_1(bsh2, off2, value);
1278: off1 -= 1;
1279: off2 -= 1;
1280: }
1281: }
1282: }
1283:
1284: void
1285: shpcic_mem_copy_region_2(void *v, bus_space_handle_t bsh1,
1286: bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
1287: {
1288: u_long addr1 = bsh1 + off1;
1289: u_long addr2 = bsh2 + off2;
1290: uint16_t value;
1291:
1292: if (addr1 >= addr2) { /* src after dest: copy forward */
1293: while (count--) {
1294: value = __shpcic_mem_read_2(bsh1, off1);
1295: __shpcic_mem_write_2(bsh2, off2, value);
1296: off1 += 2;
1297: off2 += 2;
1298: }
1299: } else { /* dest after src: copy backwards */
1300: off1 += (count - 1) * 2;
1301: off2 += (count - 1) * 2;
1302: while (count--) {
1303: value = __shpcic_mem_read_2(bsh1, off1);
1304: __shpcic_mem_write_2(bsh2, off2, value);
1305: off1 -= 2;
1306: off2 -= 2;
1307: }
1308: }
1309: }
1310:
1311: void
1312: shpcic_mem_copy_region_4(void *v, bus_space_handle_t bsh1,
1313: bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, bus_size_t count)
1314: {
1315: u_long addr1 = bsh1 + off1;
1316: u_long addr2 = bsh2 + off2;
1317: uint32_t value;
1318:
1319: if (addr1 >= addr2) { /* src after dest: copy forward */
1320: while (count--) {
1321: value = __shpcic_mem_read_4(bsh1, off1);
1322: __shpcic_mem_write_4(bsh2, off2, value);
1323: off1 += 4;
1324: off2 += 4;
1325: }
1326: } else { /* dest after src: copy backwards */
1327: off1 += (count - 1) * 4;
1328: off2 += (count - 1) * 4;
1329: while (count--) {
1330: value = __shpcic_mem_read_4(bsh1, off1);
1331: __shpcic_mem_write_4(bsh2, off2, value);
1332: off1 -= 4;
1333: off2 -= 4;
1334: }
1335: }
1336: }
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