Annotation of sys/arch/sh/dev/scifreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: scifreg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $ */
2: /* $NetBSD: scifreg.h,v 1.10 2006/02/18 00:41:32 uwe Exp $ */
3:
4: /*-
5: * Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. The name of the author may not be used to endorse or promote products
16: * derived from this software without specific prior written permission.
17: *
18: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27: * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28: */
29:
30: /*
31: * Serial Communication Interface with FIFO (SCIF)
32: */
33:
34: #define SH3_SCIF0_BASE 0xa4000150
35: #define SH3_SCIF1_BASE 0xa4000140
36:
37: #define SH4_SCIF_BASE 0xffe80000
38:
39: #ifdef SH3
40:
41: /* SH3 definitions */
42:
43: #define SCIF_SMR 0x0 /* serial mode */
44: #define SCIF_BRR 0x2 /* bit rate */
45: #define SCIF_SCR 0x4 /* serial control */
46: #define SCIF_FTDR 0x6 /* transmit fifo data */
47: #define SCIF_SSR 0x8 /* serial status */
48: #define SCIF_FRDR 0xa /* receive fifo data */
49: #define SCIF_FCR 0xc /* fifo control */
50: #define SCIF_FDR 0xe /* fifo data count set */
51:
52: #define SHREG_SCSMR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_SMR))
53: #define SHREG_SCBRR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_BRR))
54: #define SHREG_SCSCR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_SCR))
55: #define SHREG_SCFTDR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_FTDR))
56: #define SHREG_SCSSR2 (*(volatile uint16_t *)(SH3_SCIF0_BASE + SCIF_SSR))
57: #define SHREG_SCFRDR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_FRDR))
58: #define SHREG_SCFCR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_FCR))
59: #define SHREG_SCFDR2 (*(volatile uint16_t *)(SH3_SCIF0_BASE + SCIF_FDR))
60:
61: #else /* !SH3 */
62:
63: /* SH4 definitions */
64:
65: #define SCIF_SMR 0x00 /* serial mode */
66: #define SCIF_BRR 0x04 /* bit rate */
67: #define SCIF_SCR 0x08 /* serial control */
68: #define SCIF_FTDR 0x0c /* transmit fifo data */
69: #define SCIF_SSR 0x10 /* serial status */
70: #define SCIF_FRDR 0x14 /* receive fifo data */
71: #define SCIF_FCR 0x18 /* fifo control */
72: #define SCIF_FDR 0x1c /* fifo data count set */
73:
74: #define SCIF_SPTR 0x20 /* seial port */
75: #define SCIF_LSR 0x24 /* line status */
76:
77: #define SHREG_SCSMR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SMR))
78: #define SHREG_SCBRR2 (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_BRR))
79: #define SHREG_SCSCR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SCR))
80: #define SHREG_SCFTDR2 (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_FTDR))
81: #define SHREG_SCSSR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SSR))
82: #define SHREG_SCFRDR2 (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_FRDR))
83: #define SHREG_SCFCR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FCR))
84: #define SHREG_SCFDR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FDR))
85:
86: #define SHREG_SCSPTR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SPTR))
87: #define SHREG_SCLSR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_LSR))
88:
89: /* alias */
90: #define SHREG_SCSFDR2 SHREG_SCFTDR2
91: #define SHREG_SCFSR2 SHREG_SCSSR2
92:
93: #define SCSPTR2_RTSIO 0x0080
94: #define SCSPTR2_RTSDT 0x0040
95: #define SCSPTR2_CTSIO 0x0020
96: #define SCSPTR2_CTSDT 0x0010
97: #define SCSPTR2_SCKIO 0x0008
98: #define SCSPTR2_SCKDT 0x0004
99: #define SCSPTR2_SPB2IO 0x0002
100: #define SCSPTR2_SPB2DT 0x0001
101:
102: #define SCLSR2_ORER 0x0001 /* overrun error */
103:
104: #endif /* !SH3 */
105:
106: /* SMR: serial mode */
107: #define SCSMR2_CHR 0x40 /* character width (set = 7bit) */
108: #define SCSMR2_PE 0x20 /* Parity Enable */
109: #define SCSMR2_O 0x10 /* parity mode Odd */
110: #define SCSMR2_STOP 0x08 /* STOP bit (set = 2 stop bits) */
111: #define SCSMR2_CKS1 0x02 /* ClocK Select 1 */
112: #define SCSMR2_CKS0 0x01 /* ClocK Select 0 */
113:
114: /* SMR: serial mode (for IrDA) */
115: #define SCSMR2_IRMOD 0x80 /* IrDA mode */
116: #define SCSMR2_ICK3 0x40
117: #define SCSMR2_ICK2 0x20
118: #define SCSMR2_ICK1 0x10
119: #define SCSMR2_ICK0 0x08
120: #define SCSMR2_PSEL 0x04 /* Pulse width SELelect */
121:
122: /* SCR: serial control */
123: #define SCSCR2_TIE 0x80 /* Transmit Interrupt Enable */
124: #define SCSCR2_RIE 0x40 /* Recieve Interrupt Enable */
125: #define SCSCR2_TE 0x20 /* Transmit Enable */
126: #define SCSCR2_RE 0x10 /* Receive Enable */
127: #define SCSCR2_CKE1 0x02 /* ClocK Enable 1 */
128: #define SCSCR2_CKE0 0x01 /* ClocK Enable 0 (not in sh4) */
129:
130: /* SSR: serial status */
131: #define SCSSR2_ER 0x0080 /* ERror */
132: #define SCSSR2_TEND 0x0040 /* Transmit END */
133: #define SCSSR2_TDFE 0x0020 /* Transmit Data Fifo Empty */
134: #define SCSSR2_BRK 0x0010 /* BReaK detection */
135: #define SCSSR2_FER 0x0008 /* Framing ERror */
136: #define SCSSR2_PER 0x0004 /* Parity ERror */
137: #define SCSSR2_RDF 0x0002 /* Recieve fifo Data Full */
138: #define SCSSR2_DR 0x0001 /* Data Ready */
139:
140: /* FCR: fifo control */
141: #define SCFCR2_RTRG1 0x80 /* Receive TRiGger 1 */
142: #define SCFCR2_RTRG0 0x40 /* Receive TRiGger 0 */
143: #define SCFCR2_TTRG1 0x20 /* Transmit TRiGger 1 */
144: #define SCFCR2_TTRG0 0x10 /* Transmit TRiGger 0 */
145: #define SCFCR2_MCE 0x08 /* Modem Control Enable */
146: #define SCFCR2_TFRST 0x04 /* Transmit Fifo register ReSeT */
147: #define SCFCR2_RFRST 0x02 /* Receive Fifo register ReSeT */
148: #define SCFCR2_LOOP 0x01 /* LOOP back test */
149:
150: #define FIFO_RCV_TRIGGER_1 0x00
151: #define FIFO_RCV_TRIGGER_4 0x40
152: #define FIFO_RCV_TRIGGER_8 0x80
153: #define FIFO_RCV_TRIGGER_14 0xc0
154:
155: #define FIFO_XMT_TRIGGER_8 0x00
156: #define FIFO_XMT_TRIGGER_4 0x10
157: #define FIFO_XMT_TRIGGER_2 0x20
158: #define FIFO_XMT_TRIGGER_1 0x30
159:
160: /* FDR: fifo data count set */
161: #define SCFDR2_TXCNT 0xff00 /* Tx CouNT */
162: #define SCFDR2_RECVCNT 0x00ff /* Rx CouNT */
163: #define SCFDR2_TXF_FULL 0x1000 /* Tx FULL */
164: #define SCFDR2_RXF_EPTY 0x0000 /* Rx EMPTY */
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